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AJvYcCWWb+c0xqmU44rH1WnRkNYP1ln1jJ1CrzEwODBRCIdZrfOcMmryEp9srH3outy/ofwUTk25Ithj5JQflBU=@vger.kernel.org X-Gm-Message-State: AOJu0Yz1cA3GhGsqtELNy8j+A64w3fvH2khklzO0ySUb3k2Pbp2VDIyk ol8RbrbZZUGHm46fy0CoZcTzJfSi79RUSk2fjPOipltycz2OZKRvkCxyB5uRt0scMCURcmovtot 0fX1jIA== X-Received: from plef22.prod.google.com ([2002:a17:902:f396:b0:2aa:f9fe:3355]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:234e:b0:2aa:e3f7:a945 with SMTP id d9443c01a7336-2ad74549d90mr81342145ad.49.1771865700687; Mon, 23 Feb 2026 08:55:00 -0800 (PST) Date: Mon, 23 Feb 2026 08:54:59 -0800 In-Reply-To: <5a826ae2c3549303c205817520623fe3fc4699ec.camel@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260219002241.2908563-1-seanjc@google.com> <5a826ae2c3549303c205817520623fe3fc4699ec.camel@intel.com> Message-ID: Subject: Re: [PATCH] KVM: x86/mmu: Don't create SPTEs for addresses that aren't mappable From: Sean Christopherson To: Kai Huang Cc: "pbonzini@redhat.com" , Yan Y Zhao , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Rick P Edgecombe , "yosry.ahmed@linux.dev" Content-Type: text/plain; charset="us-ascii" On Mon, Feb 23, 2026, Kai Huang wrote: > > > @@ -3540,6 +3540,14 @@ static int kvm_handle_noslot_fault(struct kvm_vcpu *vcpu, > > if (unlikely(fault->gfn > kvm_mmu_max_gfn())) > > return RET_PF_EMULATE; > > > > + /* > > + * Similarly, if KVM can't map the faulting address, don't attempt to > > + * install a SPTE because KVM will effectively truncate the address > > + * when walking KVM's page tables. > > + */ > > + if (unlikely(fault->addr & vcpu->arch.mmu->unmappable_mask)) > > + return RET_PF_EMULATE; > > + > > return RET_PF_CONTINUE; > > } > > > > @@ -4681,6 +4689,11 @@ static int kvm_mmu_faultin_pfn(struct kvm_vcpu *vcpu, > > return RET_PF_RETRY; > > } > > > > + if (fault->addr & vcpu->arch.mmu->unmappable_mask) { > > + kvm_mmu_prepare_memory_fault_exit(vcpu, fault); > > + return -EFAULT; > > + } > > + > > If we forget the case of shadow paging, do you think we should explicitly > strip the shared bit? > > I think the MMU code currently always treats the shared bit as "mappable" > (as long as the real GPA is mappable), so logically it's better to strip the > shared bit first before checking the GPA. But in practice there's no > problem because only TDX uses shared bit and it is within the 'mappable' > bits. I don't think so? Because even though the SHARED bit has special semantics, it's still very much an address bit in the current architecture. > But the odd is if the fault->addr is L2 GPA or L2 GVA, then the shared bit > (which is concept of L1 guest) doesn't apply to it. > > Btw, from hardware's point of view, does EPT/NPT silently drops high > unmappable bits of GPA or it generates some kinda EPT violation/misconfig? EPT violation. The SDM says: With 4-level EPT, bits 51:48 of the guest-physical address must all be zero; otherwise, an EPT violation occurs (see Section 30.3.3). I can't find anything in the APM (shocker, /s) that clarifies the exact NPT behavior. It barely even alludes to the use of hCR4.LA57 for controlling the depth of the walk. But I'm fairly certain NPT behaves identically.