[PATCH 02/21] perf/x86/intel/lbr: Add pointers for LBR enable and disable

kan.liang
2020-06-19T14:07:51Z

The method to enable and disable Architectural LBR is different from
the previous model-specific LBR. Perf has to implement different
functions.

The function pointers for LBR enable and disable are introduced. Perf
should initialize the corresponding functions at boot time.

The current model-specific LBR functions are set as default.

The __intel_pmu_lbr_disable() and __intel_pmu_lbr_enable() are not
static functions anymore. The prefix "__" is removed from the name.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 6 ++++++
arch/x86/events/intel/lbr.c | 8 ++++----
arch/x86/events/perf_event.h | 7 +++++++
3 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 332954c..56966fc 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3951,6 +3951,9 @@ static __initconst const struct x86_pmu core_pmu = {
.cpu_dead = intel_pmu_cpu_dead,

.check_period = intel_pmu_check_period,
+
+ .lbr_enable = intel_pmu_lbr_enable,
+ .lbr_disable = intel_pmu_lbr_disable,
};

static __initconst const struct x86_pmu intel_pmu = {
@@ -3996,6 +3999,9 @@ static __initconst const struct x86_pmu intel_pmu = {
.check_period = intel_pmu_check_period,

.aux_output_match = intel_pmu_aux_output_match,
+
+ .lbr_enable = intel_pmu_lbr_enable,
+ .lbr_disable = intel_pmu_lbr_disable,
};

static __init void intel_clovertown_quirk(void)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 65113b1..bdd38b6 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -150,7 +150,7 @@ static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
* otherwise it becomes near impossible to get a reliable stack.
*/

-static void __intel_pmu_lbr_enable(bool pmi)
+void intel_pmu_lbr_enable(bool pmi)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
u64 debugctl, lbr_select = 0, orig_debugctl;
@@ -185,7 +185,7 @@ static void __intel_pmu_lbr_enable(bool pmi)
wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
}

-static void __intel_pmu_lbr_disable(void)
+void intel_pmu_lbr_disable(void)
{
u64 debugctl;

@@ -545,7 +545,7 @@ void intel_pmu_lbr_enable_all(bool pmi)
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

if (cpuc->lbr_users)
- __intel_pmu_lbr_enable(pmi);
+ x86_pmu.lbr_enable(pmi);
}

void intel_pmu_lbr_disable_all(void)
@@ -553,7 +553,7 @@ void intel_pmu_lbr_disable_all(void)
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

if (cpuc->lbr_users)
- __intel_pmu_lbr_disable();
+ x86_pmu.lbr_disable();
}

static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index f1cd1ca..a61a076 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -679,6 +679,9 @@ struct x86_pmu {
bool lbr_double_abort; /* duplicated lbr aborts */
bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */

+ void (*lbr_enable)(bool pmi);
+ void (*lbr_disable)(void);
+
/*
* Intel PT/LBR/BTS are exclusive
*/
@@ -1059,8 +1062,12 @@ void intel_pmu_lbr_del(struct perf_event *event);

void intel_pmu_lbr_enable_all(bool pmi);

+void intel_pmu_lbr_enable(bool pmi);
+
void intel_pmu_lbr_disable_all(void);

+void intel_pmu_lbr_disable(void);
+
void intel_pmu_lbr_read(void);

void intel_pmu_lbr_init_core(void);
--
2.7.4