Re: [PATCH 3/3] can: flexcan: handle S32G2/S32G3 separate interrupt lines

[Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>]

On 11/20/2024 12:01 PM, Marc Kleine-Budde wrote:
> On 20.11.2024 11:01:25, Ciprian Marian Costea wrote:
>> On 11/20/2024 10:52 AM, Marc Kleine-Budde wrote:
>>> On 19.11.2024 10:10:53, Ciprian Costea wrote:
>>>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>>
>>>> On S32G2/S32G3 SoC, there are separate interrupts
>>>> for state change, bus errors, MBs 0-7 and MBs 8-127 respectively.
>>>>
>>>> In order to handle this FlexCAN hardware particularity, reuse
>>>> the 'FLEXCAN_QUIRK_NR_IRQ_3' quirk provided by mcf5441x's irq
>>>> handling support.
>>>>
>>>> Additionally, introduce 'FLEXCAN_QUIRK_SECONDARY_MB_IRQ' quirk,
>>>> which can be used in case there are two separate mailbox ranges
>>>> controlled by independent hardware interrupt lines, as it is
>>>> the case on S32G2/S32G3 SoC.
>>>
>>> Does the mainline driver already handle the 2nd mailbox range? Is there
>>> any downstream code yet?
>>>
>>> Marc
>>>
>>
>> Hello Marc,
>>
>> The mainline driver already handles the 2nd mailbox range (same
>> 'flexcan_irq') is used. The only difference is that for the 2nd mailbox
>> range a separate interrupt line is used.
> 
> AFAICS the IP core supports up to 128 mailboxes, though the driver only
> supports 64 mailboxes. Which mailboxes do you mean by the "2nd mailbox
> range"? What about mailboxes 64..127, which IRQ will them?
> 

On S32G the following is the mapping between FlexCAN IRQs and mailboxes:
- IRQ line X -> Mailboxes 0-7
- IRQ line Y -> Mailboxes 8-127 (Logical OR of Message Buffer Interrupt 
lines 127 to 8)

By 2nd range, I was refering to Mailboxes 8-127.



>> I do plan to upstream more patches to the flexcan driver but they relate to
>> Power Management (Suspend and Resume routines) and I plan to do this in a
>> separate patchset.
> 
> regards,
> Marc
>