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AJvYcCWRCMoJT7SjF6LZTUKEx1AySCXvDFIJIFEHdxI81HYL0z8pJJeCg77tL6kbUpHImG9H5zALwyB1nSExstI=@vger.kernel.org X-Gm-Message-State: AOJu0YxSPxwrFNoUjHXd6OXYkAWBN4kNQ8qN6TrwuS56Z5jhaS8FuI2A RS2ex338Uz8KZ994dvItBM5eHRDBKmXjL1dXOJVblwcudBnd5Mlk2OitbCXBCFyFpAw+mWWWXEU qcfE90g== X-Received: from pfw6.prod.google.com ([2002:a05:6a00:a266:b0:824:a303:863c]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:6b0d:b0:394:56ae:8a7f with SMTP id adf61e73a8af0-3985908ba31mr11560818637.42.1773068768737; Mon, 09 Mar 2026 08:06:08 -0700 (PDT) Date: Mon, 9 Mar 2026 08:06:07 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260307011619.2324234-4-yosry@kernel.org> <34cbc227-f01f-4d4b-b6ab-19bcb02d7e3c@citrix.com> Message-ID: Subject: Re: [PATCH v2 3/3] KVM: SVM: Advertise Translation Cache Extensions to userspace From: Sean Christopherson To: Yosry Ahmed Cc: Andrew Cooper , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, pbonzini@redhat.com, venkateshs@chromium.org, venkateshs@google.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Mon, Mar 09, 2026, Yosry Ahmed wrote: > On Fri, Mar 6, 2026 at 5:54=E2=80=AFPM Andrew Cooper wrote: > > > > > From: Venkatesh Srinivas > > > > > > TCE augments the behavior of TLB invalidating instructions (INVLPG, > > > INVLPGB, and INVPCID) to only invalidate translations for relevant > > > intermediate mappings to the address range, rather than ALL intermdia= te > > > translations. > > > > > > The Linux kernel has been setting EFER.TCE if supported by the CPU si= nce > > > commit 440a65b7d25f ("x86/mm: Enable AMD translation cache extensions= "), > > > as it may improve performance. > > > > > > KVM does not need to do anything to virtualize the feature, only > > > advertise it and allow setting EFER.TCE. If a TLB invalidating > > > instruction is not intercepted, it will behave according to the guest= 's > > > setting of EFER.TCE as the value will be loaded on VM-Enter. Otherwis= e, > > > KVM's emulation may invalidate more TLB entries, which is perfectly f= ine > > > as the CPU is allowed to invalidate more TLB entries that it strictly > > > needs to. > > > > > > Advertise X86_FEATURE_TCE to userspace, and allow the guest to set > > > EFER.TCE if available. > > > > > > Signed-off-by: Venkatesh Srinivas > > > Co-developed-by: Yosry Ahmed > > > Signed-off-by: Yosry Ahmed > > > > I'll repeat what I said on that referenced patch. > > > > What's the point? AMD have said that TCE doesn't exist any more; it's = a > > bit that's no longer wired into anything. > > > > You've got to get to pre-Zen hardware before this has any behavioural > > effect, at which point the breath of testing is almost 0. >=20 > Oh, I did not know that, thanks for pointing it out. >=20 > I'll leave it up to Sean whether to pick this up (because Linux guests > still set the bit), just pick up patches 1-2 as cleanups, or drop this > entirely. I'll grab 1-2 and leave 3 alone, at least for now. It _should_ do no harm,= but it would really suck to discover that pre-Zen hardware has a TLB bug that a= ffects TCE, or worse, affects TCE but only for ASID!=3D0 translations or something= . If new CPUs ever use TCE, it'll be trivial to enable at that time.