From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.ilvokhin.com (mail.ilvokhin.com [178.62.254.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D96C52E54AA for ; Mon, 9 Mar 2026 18:12:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.62.254.231 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773079955; cv=none; b=fFtFqpDjEzuiiWlFgUh1qTgIEdkQ37uYTUVJijaC83Zn8cv9uo5ZcguX71oKwpzKKY2bVNRJUCwLnlYhZmJQKeVcq2Pp2cz+IdGfztiAJVdThXdDl/NYB5bNEFBRuAzv6nFNNlGtqRUA+1HazJ6yDrKbgbtNgKkC+F6hzYk1Qms= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773079955; c=relaxed/simple; bh=+hAMDeA0EySi5lRzdFrGvKu5Sv0rqfSrvRhBYh7OcCM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=r82dJ8q1SYuVIY7X0w3Pg/iRh9Ey8stSbLel/0hvxCKKLhDDnadejOYxyGCk4YgP/YBwg7tH4wTlXClKtP0WuEq21XgKg4tQuWVZzCqCIBuu1andiDRHkMUVMcpPsXGV6MJCoTciiGmavR6eudQogLVH03iquM3knJAjIQI7KQU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ilvokhin.com; spf=pass smtp.mailfrom=ilvokhin.com; dkim=pass (1024-bit key) header.d=ilvokhin.com header.i=@ilvokhin.com header.b=rguBfire; arc=none smtp.client-ip=178.62.254.231 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ilvokhin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ilvokhin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ilvokhin.com header.i=@ilvokhin.com header.b="rguBfire" Received: from shell.ilvokhin.com (shell.ilvokhin.com [138.68.190.75]) (Authenticated sender: d@ilvokhin.com) by mail.ilvokhin.com (Postfix) with ESMTPSA id E8F45B3720; Mon, 09 Mar 2026 18:12:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ilvokhin.com; s=mail; t=1773079952; bh=iWKaeJ/CD0xl+jX7xXIIvWXb+Iq6Oj/bLOt1FqoDpE4=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=rguBfire3dXGuuqsZsBxfI2ywkFc7zyqSnfniJNu6xNmfna9el0c/V27h8xmAVQWY LkNc9VgBBkiyHP7h9Cydw3xbiMaBvaipt8Rb04tTx4eY5GFcjL/Lp0E6V4PthLjV0D p3L2YupK5XE6KyVSV74/EA9ZL6JiAEVc1F2jGnM4= Date: Mon, 9 Mar 2026 18:12:30 +0000 From: Dmitry Ilvokhin To: Thomas Gleixner Cc: LKML , x86@kernel.org, Neil Horman Subject: Re: [patch 04/14] x86/irq: Make irqstats array based Message-ID: References: <20260303150539.513068586@kernel.org> <20260303154548.218256740@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260303154548.218256740@kernel.org> On Wed, Mar 04, 2026 at 07:55:45PM +0100, Thomas Gleixner wrote: > Having the x86 specific interrupt statistics as a data structure with > individual members instead of an array is just stupid as it requires > endless copy and paste in arch_show_interrupts() and arch_irq_stat_cpu(), > where the latter does not even take the latest interrupt additions into > account. The resulting #ifdef orgy is just disgusting. > > Convert it to an array of counters, which does not make a difference in the > actual interrupt hotpath increment as the array index is constant and > therefore not any different than the member based access. > > But in arch_show_interrupts() and arch_irq_stat_cpu() this just turns into > a loop, which reduces the text size by ~2k (~12%): > > text data bss dec hex filename > 19643 15250 904 35797 8bd5 ../build/arch/x86/kernel/irq.o > 17355 15250 904 33509 82e5 ../build/arch/x86/kernel/irq.o > > Adding a new vector or software counter only requires to update the table > and everything just works. Using the core provided emit function which > speeds up 0 outputs makes it significantly faster. > > Signed-off-by: Thomas Gleixner > --- > arch/x86/events/amd/core.c | 2 > arch/x86/events/amd/ibs.c | 2 > arch/x86/events/core.c | 2 > arch/x86/events/intel/core.c | 2 > arch/x86/events/intel/knc.c | 2 > arch/x86/events/intel/p4.c | 2 > arch/x86/events/zhaoxin/core.c | 2 > arch/x86/hyperv/hv_init.c | 2 > arch/x86/include/asm/hardirq.h | 69 ++++++---- > arch/x86/include/asm/mce.h | 3 > arch/x86/kernel/apic/apic.c | 4 > arch/x86/kernel/apic/ipi.c | 2 > arch/x86/kernel/cpu/acrn.c | 2 > arch/x86/kernel/cpu/mce/amd.c | 2 > arch/x86/kernel/cpu/mce/core.c | 8 - > arch/x86/kernel/cpu/mce/threshold.c | 2 > arch/x86/kernel/cpu/mshyperv.c | 4 > arch/x86/kernel/irq.c | 227 ++++++++++-------------------------- > arch/x86/kernel/irq_work.c | 2 > arch/x86/kernel/kvm.c | 2 > arch/x86/kernel/nmi.c | 4 > arch/x86/kernel/smp.c | 6 > arch/x86/mm/tlb.c | 2 > arch/x86/xen/enlighten_hvm.c | 2 > arch/x86/xen/enlighten_pv.c | 2 > arch/x86/xen/smp.c | 6 > arch/x86/xen/smp_pv.c | 2 > 27 files changed, 135 insertions(+), 232 deletions(-) > [...] > - if (x86_platform_ipi_callback) { > - seq_printf(p, "%*s:", prec, "PLT"); > - for_each_online_cpu(j) > - put_decimal(p, irq_stats(j)->x86_platform_ipis); > - seq_puts(p, " Platform interrupts\n"); > - } > + ISS(APIC_TIMER, "LOC", " Local timer interrupts\n"), > + ISS(SPURIOUS, "SPU", " Spurious interrupts\n"), > + ISS(APIC_PERF, "PMI", " Performance monitoring interrupts\n"), > + ISS(IRQ_WORK, "IWI", " IRQ work interrupts\n"), > + ISS(ICR_READ_RETRY, "RTR", " APIC ICR read retries\n"), > + ISS(X86_PLATFORM_IPI, "PLT", " Platform interrupts\n"), The old code only showed "PLT" when x86_platform_ipi_callback was set, but with ISS() this is now unconditional. Is this intentional? [...] > - seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); > -#if defined(CONFIG_X86_IO_APIC) > - seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count)); > + ITS(HYPERV_REENLIGHTMENT, "HRE", " Hyper-V reenlightment interrupts\n"), HYPERV_REENLIGHTMENT doesn't match the enum (HYPERV_REENLIGHTENMENT). This should break the build with CONFIG_HYPERV=y. There is also a same typo in text description. > + seq_printf(p, "ERR: %10u\n", (unsigned int) atomic_read(&irq_err_count)); > + if (IS_ENABLED(CONFIG_X86_IO_APIC)) > + seq_printf(p, "MIS: %10u\n", (unsigned int) atomic_read(&irq_mis_count)); This drops the prec-based alignment for ERR and MIS.