From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A5C5E345736 for ; Fri, 27 Feb 2026 16:34:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772210050; cv=none; b=o6lB06Uol6l2RNVIHJG4O1Lv7sB/Kb8n7YpcFkVW26zGHfhOk9vDOREcB34HMH9eXNLEWYrkCsuK4oRvPT1UL+bXJ7Kb+ujIbzWnpP6WxXXFNhMJ6o9DZhb1yzH6hY70XcwuxEcPddKKfp0SyuA9fPJyyOAEmNHzgLuqX24IcoA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772210050; c=relaxed/simple; bh=H3MoXUcEhzgCP7QxJSxpOfnc0Zt6LXTe+bMhChJhLCU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Y1buOuYfNFO9Vii0QulSDCjDuZNDwWYveEJOrMWWZwoqvb0uPMN4bbwSqjUcHbLGaN6VFYhsQCkmD3JhgAdkr6VIb1tr8Zc/fk6nPqgkwI6hxiFWo+qU4AH5NiPSroSAf03NNs6sT9uC/wwGD6UIqKRLP3mOJ1DAs/0ac8Ua8IA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B4EA614BF; Fri, 27 Feb 2026 08:34:01 -0800 (PST) Received: from arm.com (arrakis.cambridge.arm.com [10.1.197.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 305C43F73B; Fri, 27 Feb 2026 08:34:07 -0800 (PST) Date: Fri, 27 Feb 2026 16:34:04 +0000 From: Catalin Marinas To: Jisheng Zhang Cc: Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: runtime-const: save one instruction when ARM64_VA_BITS <= 48 Message-ID: References: <20260225144613.30846-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260225144613.30846-1-jszhang@kernel.org> On Wed, Feb 25, 2026 at 10:46:13PM +0800, Jisheng Zhang wrote: > Currently, the runtime_const_ptr() uses 4 instructions to move a long > imm to GP, but when ARM64_VA_BITS <= 48(which is true for android and > armbian), the top 8bits of runtime cont ptr is all '1', so we can make ^^^^^ 8 or 16? > use of the movn instruction to construct the imm's top 8bits and lower > 16bits at the same time, thus save one instruction. This works as long as KASAN_{SW,HW}_TAGS is disabled, otherwise the top byte of a pointer is not guaranteed to be 0xff. I think both filename_init() and dcache_init() can pass tagged pointers. > diff --git a/arch/arm64/include/asm/runtime-const.h b/arch/arm64/include/asm/runtime-const.h > index be5915669d23..6797dd37d690 100644 > --- a/arch/arm64/include/asm/runtime-const.h > +++ b/arch/arm64/include/asm/runtime-const.h > @@ -7,6 +7,8 @@ > /* Sigh. You can still run arm64 in BE mode */ > #include > > +#if CONFIG_ARM64_VA_BITS > 48 You could use VA_BITS, it's shorter, though if you add the KASAN checks it's a pretty long #if to copy all over the place. We could untag the pointer but it kind of defeats the purpose of enabling KASAN in the first place. Given that Android enables KASAN_HW_TAGS by default, not sure we should bother with this change. Do you have any perf data to show that it's worth it? -- Catalin