From: Yao Zi <me@ziyao.cc>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Siddharth Vadapalli" <s-vadapalli@ti.com>,
"Hans Zhang" <18255117159@163.com>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Chen Wang" <unicorn_wang@outlook.com>,
"Manikandan K Pillai" <mpillai@cadence.com>,
"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>,
"Inochi Amaoto" <inochiama@gmail.com>,
"Han Gao" <rabenda.cn@gmail.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports
Date: Fri, 27 Feb 2026 18:24:12 +0000 [thread overview]
Message-ID: <aaHhTNEhY4ytMvAw@pie> (raw)
In-Reply-To: <20260227181925.52475-3-me@ziyao.cc>
On Fri, Feb 27, 2026 at 06:19:25PM +0000, Yao Zi wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2042 root port breaks as it advertises L0s and L1
> capabilities without supporting it.
>
> Provide a platform-specific initialization hook to override the L0s and
> L1 support advertised in LNKCAP register of SG2042 Root Ports, so it
> doesn't try to enable those states.
>
> Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> Co-authored-by: Inochi Amaoto <inochiama@gmail.com>
Oops, this should be Co-developed-by instead of Co-authored-by, sorry
for the silly mistake...
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Yao Zi <me@ziyao.cc>
Regards,
Yao Zi
next prev parent reply other threads:[~2026-02-27 18:24 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-27 18:19 [PATCH v2 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports Yao Zi
2026-02-27 18:19 ` [PATCH v2 1/2] PCI: cadence: Support platform-specific hooks for RC init/deinit Yao Zi
2026-03-03 1:08 ` Inochi Amaoto
2026-03-03 6:34 ` Chen Wang
2026-02-27 18:19 ` [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports Yao Zi
2026-02-27 18:24 ` Yao Zi [this message]
2026-03-03 1:09 ` Inochi Amaoto
2026-03-03 6:37 ` Chen Wang
2026-03-26 16:45 ` Manivannan Sadhasivam
2026-03-27 8:19 ` Yao Zi
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