[PATCH v2 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[PATCH v2 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Yao Zi]

After talking to Inochi privately, I'll take the patch instead.

This series defines initialization/de-initialization hooks for Cadence
PCIe host driver to allow platform drivers to override RC ports
properties, and provides such an initialization hook in SG2042 PCIe
driver to clear PCI_EXP_LNKCAP_ASPMS since SG2042's implementation is
broken.

I've considered to re-write LNKCAP after cdns_pcie_host_setup(), like
what has been done in the previous version of patch. However,
cdns_pcie_host_setup() performs pci_host_probe(), which finally invokes
set_pcie_port_type() on the root port. It reads ASPM-related LNKCAP,
which might lead to dangling pci_dev.aspm_{l0s,l1}_support values.
Early PCI device fixup won't work for similar reasons, since the fixup
is performed in pci_setup_device() after calling set_pcie_port_type().

It's hard to fix up the LNKCAP earlier than invokation of
cdns_pcie_host_setup() in SG2042's PCIe driver, either, since
the function also performs resource allocation/mapping, and we have no
access to the RC registers before it returns.

The safest solution which also depends on no PCI subsystem
implementation detail is to have the LNKCAP fixed up right before
informing the PCI subsystem of the device through pci_host_probe(), so
here come the platform-specific hooks.

Changed from v1:
- Disable L0s/L1 capabilities through LNKCAP instead of LNKCTL
- Introduce platform-specific init/deinit hooks (new PATCH 1) to
  realiably overwrite PCIe RC properties
- Link to v1: https://lore.kernel.org/all/20260109040756.731169-2-inochiama@gmail.com/

Changed from the original patch:
- Use driver to mask the ASPM advertisement
- Separate from the following patch
  https://lore.kernel.org/all/20251225100530.1301625-1-inochiama@gmail.com

Yao Zi (2):
  PCI: cadence: Support platform-specific hooks for RC init/deinit
  PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

 .../controller/cadence/pcie-cadence-host.c    |  8 +++++++-
 drivers/pci/controller/cadence/pcie-cadence.h |  7 +++++++
 drivers/pci/controller/cadence/pcie-sg2042.c  | 20 +++++++++++++++++++
 3 files changed, 34 insertions(+), 1 deletion(-)

-- 
2.53.0

[PATCH v2 1/2] PCI: cadence: Support platform-specific hooks for RC init/deinit

[Yao Zi]

Support initialization and de-initialization hooks provided by
platform-specific drivers. Initialization ones run after everything
else has been set up for RC, but before it's probed by the PCI
subsystem, to allow platform drivers to easily override RC properties
like LNKCAP. De-initialization ones run before anything else has been
cleaned-up.

Signed-off-by: Yao Zi <me@ziyao.cc>
---
 drivers/pci/controller/cadence/pcie-cadence-host.c | 8 +++++++-
 drivers/pci/controller/cadence/pcie-cadence.h      | 7 +++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index db3154c1eccb..23ee5a9c240d 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -304,6 +304,8 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
 
 static void cdns_pcie_host_deinit(struct cdns_pcie_rc *rc)
 {
+	if (rc->ops->deinit)
+		rc->ops->deinit(rc);
 	cdns_pcie_host_deinit_address_translation(rc);
 	cdns_pcie_host_deinit_root_port(rc);
 }
@@ -316,7 +318,11 @@ int cdns_pcie_host_init(struct cdns_pcie_rc *rc)
 	if (err)
 		return err;
 
-	return cdns_pcie_host_init_address_translation(rc);
+	err = cdns_pcie_host_init_address_translation(rc);
+	if (err)
+		return err;
+
+	return rc->ops->init ? rc->ops->init(rc) : 0;
 }
 EXPORT_SYMBOL_GPL(cdns_pcie_host_init);
 
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 443033c607d7..7d8f8e87915b 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -100,6 +100,11 @@ struct cdns_pcie {
 	const  struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
 };
 
+struct cdns_pcie_rc_ops {
+	int	(*init)(struct cdns_pcie_rc *rc);
+	void	(*deinit)(struct cdns_pcie_rc *rc);
+};
+
 /**
  * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
  * @pcie: Cadence PCIe controller
@@ -115,6 +120,7 @@ struct cdns_pcie {
  * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
  * @ecam_supported: Whether the ECAM is supported
  * @no_inbound_map: Whether inbound mapping is supported
+ * @ops: Platform-specific hooks to initialize/de-initialize PCIe Root Complex
  */
 struct cdns_pcie_rc {
 	struct cdns_pcie	pcie;
@@ -127,6 +133,7 @@ struct cdns_pcie_rc {
 	unsigned int		quirk_detect_quiet_flag:1;
 	unsigned int            ecam_supported:1;
 	unsigned int            no_inbound_map:1;
+	const struct cdns_pcie_rc_ops *ops;
 };
 
 /**
-- 
2.53.0

[PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Yao Zi]

Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
states for devicetree platforms") force enable ASPM on all device tree
platform, the SG2042 root port breaks as it advertises L0s and L1
capabilities without supporting it.

Provide a platform-specific initialization hook to override the L0s and
L1 support advertised in LNKCAP register of SG2042 Root Ports, so it
doesn't try to enable those states.

Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
Co-authored-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Yao Zi <me@ziyao.cc>
---
 drivers/pci/controller/cadence/pcie-sg2042.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
index 0c50c74d03ee..3142f82bd393 100644
--- a/drivers/pci/controller/cadence/pcie-sg2042.c
+++ b/drivers/pci/controller/cadence/pcie-sg2042.c
@@ -32,6 +32,25 @@ static struct pci_ops sg2042_pcie_child_ops = {
 	.write		= pci_generic_config_write,
 };
 
+static int sg2042_pcie_disable_l0s_l1(struct cdns_pcie_rc *rc)
+{
+	struct cdns_pcie *pcie = &rc->pcie;
+	u32 pcie_lnkcap_off;
+	u32 lnkcap;
+
+	pcie_lnkcap_off = CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP;
+
+	lnkcap = cdns_pcie_rp_readw(pcie, pcie_lnkcap_off);
+	lnkcap &= ~PCI_EXP_LNKCAP_ASPMS;
+	cdns_pcie_rp_writew(pcie, pcie_lnkcap_off, lnkcap);
+
+	return 0;
+}
+
+static const struct cdns_pcie_rc_ops sg2042_pcie_rc_ops = {
+	.init	= sg2042_pcie_disable_l0s_l1,
+};
+
 static int sg2042_pcie_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -48,6 +67,7 @@ static int sg2042_pcie_probe(struct platform_device *pdev)
 	bridge->child_ops = &sg2042_pcie_child_ops;
 
 	rc = pci_host_bridge_priv(bridge);
+	rc->ops = &sg2042_pcie_rc_ops;
 	pcie = &rc->pcie;
 	pcie->dev = dev;
 
-- 
2.53.0

Re: [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Yao Zi]

On Fri, Feb 27, 2026 at 06:19:25PM +0000, Yao Zi wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2042 root port breaks as it advertises L0s and L1
> capabilities without supporting it.
> 
> Provide a platform-specific initialization hook to override the L0s and
> L1 support advertised in LNKCAP register of SG2042 Root Ports, so it
> doesn't try to enable those states.
> 
> Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> Co-authored-by: Inochi Amaoto <inochiama@gmail.com>

Oops, this should be Co-developed-by instead of Co-authored-by, sorry
for the silly mistake...

> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Yao Zi <me@ziyao.cc>

Regards,
Yao Zi

Re: [PATCH v2 1/2] PCI: cadence: Support platform-specific hooks for RC init/deinit

[Inochi Amaoto]

On Fri, Feb 27, 2026 at 06:19:24PM +0000, Yao Zi wrote:
> Support initialization and de-initialization hooks provided by
> platform-specific drivers. Initialization ones run after everything
> else has been set up for RC, but before it's probed by the PCI
> subsystem, to allow platform drivers to easily override RC properties
> like LNKCAP. De-initialization ones run before anything else has been
> cleaned-up.
> 
> Signed-off-by: Yao Zi <me@ziyao.cc>
> ---
>  drivers/pci/controller/cadence/pcie-cadence-host.c | 8 +++++++-
>  drivers/pci/controller/cadence/pcie-cadence.h      | 7 +++++++
>  2 files changed, 14 insertions(+), 1 deletion(-)
> 

LGTM.

Reviewed-by: Inochi Amaoto <inochiama@gmail.com>

Regards,
Inochi

> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index db3154c1eccb..23ee5a9c240d 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -304,6 +304,8 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
>  
>  static void cdns_pcie_host_deinit(struct cdns_pcie_rc *rc)
>  {
> +	if (rc->ops->deinit)
> +		rc->ops->deinit(rc);
>  	cdns_pcie_host_deinit_address_translation(rc);
>  	cdns_pcie_host_deinit_root_port(rc);
>  }
> @@ -316,7 +318,11 @@ int cdns_pcie_host_init(struct cdns_pcie_rc *rc)
>  	if (err)
>  		return err;
>  
> -	return cdns_pcie_host_init_address_translation(rc);
> +	err = cdns_pcie_host_init_address_translation(rc);
> +	if (err)
> +		return err;
> +
> +	return rc->ops->init ? rc->ops->init(rc) : 0;
>  }
>  EXPORT_SYMBOL_GPL(cdns_pcie_host_init);
>  
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 443033c607d7..7d8f8e87915b 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -100,6 +100,11 @@ struct cdns_pcie {
>  	const  struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
>  };
>  
> +struct cdns_pcie_rc_ops {
> +	int	(*init)(struct cdns_pcie_rc *rc);
> +	void	(*deinit)(struct cdns_pcie_rc *rc);
> +};
> +
>  /**
>   * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
>   * @pcie: Cadence PCIe controller
> @@ -115,6 +120,7 @@ struct cdns_pcie {
>   * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
>   * @ecam_supported: Whether the ECAM is supported
>   * @no_inbound_map: Whether inbound mapping is supported
> + * @ops: Platform-specific hooks to initialize/de-initialize PCIe Root Complex
>   */
>  struct cdns_pcie_rc {
>  	struct cdns_pcie	pcie;
> @@ -127,6 +133,7 @@ struct cdns_pcie_rc {
>  	unsigned int		quirk_detect_quiet_flag:1;
>  	unsigned int            ecam_supported:1;
>  	unsigned int            no_inbound_map:1;
> +	const struct cdns_pcie_rc_ops *ops;
>  };
>  
>  /**
> -- 
> 2.53.0
> 

Re: [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Inochi Amaoto]

On Fri, Feb 27, 2026 at 06:24:12PM +0000, Yao Zi wrote:
> On Fri, Feb 27, 2026 at 06:19:25PM +0000, Yao Zi wrote:
> > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > states for devicetree platforms") force enable ASPM on all device tree
> > platform, the SG2042 root port breaks as it advertises L0s and L1
> > capabilities without supporting it.
> > 
> > Provide a platform-specific initialization hook to override the L0s and
> > L1 support advertised in LNKCAP register of SG2042 Root Ports, so it
> > doesn't try to enable those states.
> > 
> > Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> > Co-authored-by: Inochi Amaoto <inochiama@gmail.com>
> 
> Oops, this should be Co-developed-by instead of Co-authored-by, sorry
> for the silly mistake...
> 
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > Signed-off-by: Yao Zi <me@ziyao.cc>
> 
> Regards,
> Yao Zi

Thanks, and this patch is LGTM.

With the tag fixed:

Reviewed-by: Inochi Amaoto <inochiama@gmail.com>

Regards,
Inochi

Re: [PATCH v2 1/2] PCI: cadence: Support platform-specific hooks for RC init/deinit

[Chen Wang]

On 2/28/2026 2:19 AM, Yao Zi wrote:
> Support initialization and de-initialization hooks provided by
> platform-specific drivers. Initialization ones run after everything
> else has been set up for RC, but before it's probed by the PCI
> subsystem, to allow platform drivers to easily override RC properties
> like LNKCAP. De-initialization ones run before anything else has been
> cleaned-up.
>
> Signed-off-by: Yao Zi <me@ziyao.cc>
> ---
>   drivers/pci/controller/cadence/pcie-cadence-host.c | 8 +++++++-
>   drivers/pci/controller/cadence/pcie-cadence.h      | 7 +++++++
>   2 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index db3154c1eccb..23ee5a9c240d 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -304,6 +304,8 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
>   
>   static void cdns_pcie_host_deinit(struct cdns_pcie_rc *rc)
>   {
> +	if (rc->ops->deinit)
> +		rc->ops->deinit(rc);
>   	cdns_pcie_host_deinit_address_translation(rc);
>   	cdns_pcie_host_deinit_root_port(rc);
>   }
> @@ -316,7 +318,11 @@ int cdns_pcie_host_init(struct cdns_pcie_rc *rc)
>   	if (err)
>   		return err;
>   
> -	return cdns_pcie_host_init_address_translation(rc);
> +	err = cdns_pcie_host_init_address_translation(rc);
> +	if (err)
> +		return err;
> +
> +	return rc->ops->init ? rc->ops->init(rc) : 0;
>   }
>   EXPORT_SYMBOL_GPL(cdns_pcie_host_init);
>   
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 443033c607d7..7d8f8e87915b 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -100,6 +100,11 @@ struct cdns_pcie {
>   	const  struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
>   };
>   
> +struct cdns_pcie_rc_ops {
> +	int	(*init)(struct cdns_pcie_rc *rc);
> +	void	(*deinit)(struct cdns_pcie_rc *rc);
> +};
> +
>   /**
>    * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
>    * @pcie: Cadence PCIe controller
> @@ -115,6 +120,7 @@ struct cdns_pcie {
>    * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
>    * @ecam_supported: Whether the ECAM is supported
>    * @no_inbound_map: Whether inbound mapping is supported
> + * @ops: Platform-specific hooks to initialize/de-initialize PCIe Root Complex
>    */
>   struct cdns_pcie_rc {
>   	struct cdns_pcie	pcie;
> @@ -127,6 +133,7 @@ struct cdns_pcie_rc {
>   	unsigned int		quirk_detect_quiet_flag:1;
>   	unsigned int            ecam_supported:1;
>   	unsigned int            no_inbound_map:1;
> +	const struct cdns_pcie_rc_ops *ops;
>   };
>   
>   /**

LGTM.

Reviewd-by: Chen Wang <unicorn_wang@outlook.com>

Tested-by: Chen Wang <unicorn_wang@outlook.com>

Thanks,

Chen

Re: [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Chen Wang]

On 2/28/2026 2:19 AM, Yao Zi wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2042 root port breaks as it advertises L0s and L1
> capabilities without supporting it.
>
> Provide a platform-specific initialization hook to override the L0s and
> L1 support advertised in LNKCAP register of SG2042 Root Ports, so it
> doesn't try to enable those states.
>
> Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> Co-authored-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Yao Zi <me@ziyao.cc>
> ---
>   drivers/pci/controller/cadence/pcie-sg2042.c | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
>
> diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
> index 0c50c74d03ee..3142f82bd393 100644
> --- a/drivers/pci/controller/cadence/pcie-sg2042.c
> +++ b/drivers/pci/controller/cadence/pcie-sg2042.c
> @@ -32,6 +32,25 @@ static struct pci_ops sg2042_pcie_child_ops = {
>   	.write		= pci_generic_config_write,
>   };
>   
> +static int sg2042_pcie_disable_l0s_l1(struct cdns_pcie_rc *rc)
> +{
> +	struct cdns_pcie *pcie = &rc->pcie;
> +	u32 pcie_lnkcap_off;
> +	u32 lnkcap;
> +
> +	pcie_lnkcap_off = CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP;
> +
> +	lnkcap = cdns_pcie_rp_readw(pcie, pcie_lnkcap_off);
> +	lnkcap &= ~PCI_EXP_LNKCAP_ASPMS;
> +	cdns_pcie_rp_writew(pcie, pcie_lnkcap_off, lnkcap);
> +
> +	return 0;
> +}
> +
> +static const struct cdns_pcie_rc_ops sg2042_pcie_rc_ops = {
> +	.init	= sg2042_pcie_disable_l0s_l1,
> +};
> +
>   static int sg2042_pcie_probe(struct platform_device *pdev)
>   {
>   	struct device *dev = &pdev->dev;
> @@ -48,6 +67,7 @@ static int sg2042_pcie_probe(struct platform_device *pdev)
>   	bridge->child_ops = &sg2042_pcie_child_ops;
>   
>   	rc = pci_host_bridge_priv(bridge);
> +	rc->ops = &sg2042_pcie_rc_ops;
>   	pcie = &rc->pcie;
>   	pcie->dev = dev;
>   
LGTM.

Reviewd-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>

Thanks,

Chen

Re: [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Manivannan Sadhasivam]

On Fri, Feb 27, 2026 at 06:19:25PM +0000, Yao Zi wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2042 root port breaks as it advertises L0s and L1
> capabilities without supporting it.
> 
> Provide a platform-specific initialization hook to override the L0s and
> L1 support advertised in LNKCAP register of SG2042 Root Ports, so it
> doesn't try to enable those states.
> 
> Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> Co-authored-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Yao Zi <me@ziyao.cc>
> ---
>  drivers/pci/controller/cadence/pcie-sg2042.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
> index 0c50c74d03ee..3142f82bd393 100644
> --- a/drivers/pci/controller/cadence/pcie-sg2042.c
> +++ b/drivers/pci/controller/cadence/pcie-sg2042.c
> @@ -32,6 +32,25 @@ static struct pci_ops sg2042_pcie_child_ops = {
>  	.write		= pci_generic_config_write,
>  };
>  
> +static int sg2042_pcie_disable_l0s_l1(struct cdns_pcie_rc *rc)
> +{
> +	struct cdns_pcie *pcie = &rc->pcie;
> +	u32 pcie_lnkcap_off;
> +	u32 lnkcap;
> +
> +	pcie_lnkcap_off = CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP;
> +
> +	lnkcap = cdns_pcie_rp_readw(pcie, pcie_lnkcap_off);
> +	lnkcap &= ~PCI_EXP_LNKCAP_ASPMS;
> +	cdns_pcie_rp_writew(pcie, pcie_lnkcap_off, lnkcap);
> +

cadence-host driver already has cdns_pcie_host_init_root_port() to initialize
the Root Port. Since your intention is to modify the LNKCAP field, which belongs
to the Root Port, you should do that in cdns_pcie_host_init_root_port() instead.
I see no sg2042 specific registers used in this patch, so just set a flag in
this driver like 'broken_aspm' and clear PCI_EXP_LNKCAP_ASPMS if set in
cdns_pcie_host_init_root_port().

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Yao Zi]

On Thu, Mar 26, 2026 at 10:15:16PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Feb 27, 2026 at 06:19:25PM +0000, Yao Zi wrote:
> > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> > states for devicetree platforms") force enable ASPM on all device tree
> > platform, the SG2042 root port breaks as it advertises L0s and L1
> > capabilities without supporting it.
> > 
> > Provide a platform-specific initialization hook to override the L0s and
> > L1 support advertised in LNKCAP register of SG2042 Root Ports, so it
> > doesn't try to enable those states.
> > 
> > Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> > Co-authored-by: Inochi Amaoto <inochiama@gmail.com>
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > Signed-off-by: Yao Zi <me@ziyao.cc>
> > ---
> >  drivers/pci/controller/cadence/pcie-sg2042.c | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
> > index 0c50c74d03ee..3142f82bd393 100644
> > --- a/drivers/pci/controller/cadence/pcie-sg2042.c
> > +++ b/drivers/pci/controller/cadence/pcie-sg2042.c
> > @@ -32,6 +32,25 @@ static struct pci_ops sg2042_pcie_child_ops = {
> >  	.write		= pci_generic_config_write,
> >  };
> >  
> > +static int sg2042_pcie_disable_l0s_l1(struct cdns_pcie_rc *rc)
> > +{
> > +	struct cdns_pcie *pcie = &rc->pcie;
> > +	u32 pcie_lnkcap_off;
> > +	u32 lnkcap;
> > +
> > +	pcie_lnkcap_off = CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP;
> > +
> > +	lnkcap = cdns_pcie_rp_readw(pcie, pcie_lnkcap_off);
> > +	lnkcap &= ~PCI_EXP_LNKCAP_ASPMS;
> > +	cdns_pcie_rp_writew(pcie, pcie_lnkcap_off, lnkcap);
> > +
> 
> cadence-host driver already has cdns_pcie_host_init_root_port() to initialize
> the Root Port. Since your intention is to modify the LNKCAP field, which belongs
> to the Root Port, you should do that in cdns_pcie_host_init_root_port() instead.
> I see no sg2042 specific registers used in this patch, so just set a flag in
> this driver like 'broken_aspm' and clear PCI_EXP_LNKCAP_ASPMS if set in
> cdns_pcie_host_init_root_port().

Okay, it makes sense. Will do it in v3.

> - Mani
> 
> -- 
> மணிவண்ணன் சதாசிவம்

Regards,
Yao Zi