[PATCH 1/2] clk: samsung: pll: Fix possible truncation in a9fraco recalc rate

[PATCH 1/2] clk: samsung: pll: Fix possible truncation in a9fraco recalc rate

[Krzysztof Kozlowski]

samsung_a9fraco_recalc_rate(), unlike other functions in the unit, is
the first case dividing u64 by u64, thus it should rather use div64_u64
to avoid possible truncation.  Note that the original code did not
use remainder.

This fixes Coccinelle warning:

  clk-pll.c:1489:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202602250053.wEU1hlpY-lkp@intel.com/
Fixes: f051dc5bc8e7 ("clk: samsung: Add clock PLL support for ARTPEC-9 SoC")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
 drivers/clk/samsung/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 0d0494927e59..fdb84bcec912 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1485,7 +1485,7 @@ static unsigned long samsung_a9fraco_recalc_rate(struct clk_hw *hw,
 	/* fvco = fref * (M + K/2^24) / p * (S+1) */
 	fvco *= mdiv;
 	fvco = (fvco << 24) + kdiv;
-	do_div(fvco, ((pdiv * (sdiv + 1)) << 24));
+	fvco = div64_u64(fvco, ((pdiv * (sdiv + 1)) << 24));
 
 	return (unsigned long)fvco;
 }
-- 
2.51.0

[PATCH 2/2] clk: samsung: Use %pe format to simplify

[Krzysztof Kozlowski]

Make code printing pointer error value a bit simpler and fix coccinelle
suggestion:

  clk.c:363:16-23: WARNING: Consider using %pe to print PTR_ERR()

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
 drivers/clk/samsung/clk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 94b2bccc7d02..9d182f8c5395 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -359,8 +359,8 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
 				ctx->reg_base + list->offset, list->bit_idx,
 				list->gate_flags, &ctx->lock);
 		if (IS_ERR(clk_hw)) {
-			pr_err("%s: failed to register clock %s: %ld\n", __func__,
-				list->name, PTR_ERR(clk_hw));
+			pr_err("%s: failed to register clock %s: %pe\n", __func__,
+				list->name, clk_hw);
 			continue;
 		}
 
-- 
2.51.0

Re: [PATCH 2/2] clk: samsung: Use %pe format to simplify

[Brian Masney]

On Thu, Feb 26, 2026 at 09:54:47PM +0100, Krzysztof Kozlowski wrote:
> Make code printing pointer error value a bit simpler and fix coccinelle
> suggestion:
> 
>   clk.c:363:16-23: WARNING: Consider using %pe to print PTR_ERR()
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Reviewed-by: Brian Masney <bmasney@redhat.com>

Re: [PATCH 1/2] clk: samsung: pll: Fix possible truncation in a9fraco recalc rate

[Krzysztof Kozlowski]

On Thu, 26 Feb 2026 21:54:46 +0100, Krzysztof Kozlowski wrote:
> samsung_a9fraco_recalc_rate(), unlike other functions in the unit, is
> the first case dividing u64 by u64, thus it should rather use div64_u64
> to avoid possible truncation.  Note that the original code did not
> use remainder.
> 
> This fixes Coccinelle warning:
> 
> [...]

Applied, thanks!

[1/2] clk: samsung: pll: Fix possible truncation in a9fraco recalc rate
      https://git.kernel.org/krzk/linux/c/b8d1706ab3d99c1f96d0c9ed7d16d29b8a178d4c
[2/2] clk: samsung: Use %pe format to simplify
      https://git.kernel.org/krzk/linux/c/01df1dd3ebe0a16023138f0dc70f5decd513f32e

Best regards,
-- 
Krzysztof Kozlowski <krzk@kernel.org>

Re: [PATCH 1/2] clk: samsung: pll: Fix possible truncation in a9fraco recalc rate

[Brian Masney]

On Thu, Feb 26, 2026 at 09:54:46PM +0100, Krzysztof Kozlowski wrote:
> samsung_a9fraco_recalc_rate(), unlike other functions in the unit, is
> the first case dividing u64 by u64, thus it should rather use div64_u64
> to avoid possible truncation.  Note that the original code did not
> use remainder.
> 
> This fixes Coccinelle warning:
> 
>   clk-pll.c:1489:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead.
> 
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202602250053.wEU1hlpY-lkp@intel.com/
> Fixes: f051dc5bc8e7 ("clk: samsung: Add clock PLL support for ARTPEC-9 SoC")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Reviewed-by: Brian Masney <bmasney@redhat.com>