From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D48F71EA7D2 for ; Thu, 21 Aug 2025 07:11:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755760306; cv=none; b=FRk0FVyOILlALhPAuOUDGTm4rmXAL2mvMBwkLrGcE/G2D83mr56SioOWotbCwKHeGiikqDIipAJcowzpNVeVnKz7NRlcGL2a584qaqXCKNMEJrEd+BtDq37TegvzG4UNXRVWK4wDeA4TdAlr6E6BgIWgZhaQu9PFF1t13XxWBMc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755760306; c=relaxed/simple; bh=58RBQM6omo2HhKg7GdZdZPgexggqYZ+7Ei3/6hWVjfo=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=NyZAH8/VJ+8+2AuFKGoeurjC+96bBV73AxM4XRGIa7ZBeJMZFSi3RGDH+PwIjifHb0lezsBKG2TO4/wbgYw2+xPXttTRRSskJQ/Jm+pBP+pdlM25MDc1f9ptuFQholrFane0Ps9xnrL1zb7qGaFxokOZzS47I5SJ1NBd8jTmOh4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4c6vX559whz2Cg8n; Thu, 21 Aug 2025 15:07:17 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id DE6A41401F2; Thu, 21 Aug 2025 15:11:40 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 21 Aug 2025 15:11:40 +0800 Message-ID: Date: Thu, 21 Aug 2025 15:11:39 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH] irqchip/gic-v5: Fix kmemleak L2 IST table entries false positives Content-Language: en-US To: Lorenzo Pieralisi , CC: , Thomas Gleixner , Marc Zyngier References: <20250811135001.1333684-1-lpieralisi@kernel.org> From: Jinjie Ruan In-Reply-To: <20250811135001.1333684-1-lpieralisi@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: kwepems500001.china.huawei.com (7.221.188.70) To dggpemf500011.china.huawei.com (7.185.36.131) On 2025/8/11 21:50, Lorenzo Pieralisi wrote: > L2 IST table entries are allocated with the kmalloc interface > and their physical addresses are programmed in the GIC (either > IST base address register or L1 IST table entries) but their > virtual addresses are not stored in any kernel data structure > because they are not needed at runtime - the L2 IST table entries > are managed through system instructions but never dereferenced > directly by the driver. > [...] > > Reported-by: Jinjie Ruan > Closes: https://lore.kernel.org/lkml/cc611dda-d1e4-4793-9bb2-0eaa47277584@huawei.com/ > Signed-off-by: Lorenzo Pieralisi > Cc: Thomas Gleixner > Cc: Marc Zyngier > --- > drivers/irqchip/irq-gic-v5-irs.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-irs.c > index ad1435a858a4..e8a576f66366 100644 > --- a/drivers/irqchip/irq-gic-v5-irs.c > +++ b/drivers/irqchip/irq-gic-v5-irs.c > @@ -5,6 +5,7 @@ > > #define pr_fmt(fmt) "GICv5 IRS: " fmt > > +#include > #include > #include > #include > @@ -117,6 +118,7 @@ static int __init gicv5_irs_init_ist_linear(struct gicv5_irs_chip_data *irs_data > kfree(ist); > return ret; > } > + kmemleak_ignore(ist); > > return 0; > } > @@ -232,6 +234,7 @@ int gicv5_irs_iste_alloc(const u32 lpi) > kfree(l2ist); > return ret; > } > + kmemleak_ignore(l2ist); Reviewed-by: Jinjie Ruan > > /* > * Make sure we invalidate the cache line pulled before the IRS