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[34.83.136.168]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae83e83ad5sm28500545ad.26.2026.03.06.11.42.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 11:42:15 -0800 (PST) Date: Fri, 6 Mar 2026 19:42:11 +0000 From: Samiullah Khawaja To: Guanghui Feng Cc: baolu.lu@linux.intel.com, dwmw2@infradead.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] iommu/vt-d: fix intel iommu iotlb sync hardlockup and retry Message-ID: References: <20260306101516.3885775-1-guanghuifeng@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20260306101516.3885775-1-guanghuifeng@linux.alibaba.com> On Fri, Mar 06, 2026 at 06:15:16PM +0800, Guanghui Feng wrote: >During the qi_check_fault process after an IOMMU ITE event, >requests at odd-numbered positions in the queue are set to >QI_ABORT, only satisfying single-request submissions. However, >qi_submit_sync now supports multiple simultaneous submissions, >and can't guarantee that the wait_desc will be at an odd-numbered >position. Therefore, if an item times out, IOMMU can't re-initiate >the request, resulting in an infinite polling wait. > >This patch modifies the process by setting the status of all requests >already fetched by IOMMU and recorded as QI_IN_USE status (including >wait_desc requests) to QI_ABORT, thus enabling multiple requests to >be resubmitted. > >Signed-off-by: Guanghui Feng >Reviewed-by: Shuai Xue >--- > drivers/iommu/intel/dmar.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > >diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c >index d68c06025cac..69222dbd2af0 100644 >--- a/drivers/iommu/intel/dmar.c >+++ b/drivers/iommu/intel/dmar.c >@@ -1314,7 +1314,6 @@ static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index) > if (fault & DMA_FSTS_ITE) { > head = readl(iommu->reg + DMAR_IQH_REG); > head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; >- head |= 1; > tail = readl(iommu->reg + DMAR_IQT_REG); > tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; > >@@ -1331,7 +1330,7 @@ static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index) > do { > if (qi->desc_status[head] == QI_IN_USE) > qi->desc_status[head] = QI_ABORT; >- head = (head - 2 + QI_LENGTH) % QI_LENGTH; >+ head = (head - 1 + QI_LENGTH) % QI_LENGTH; > } while (head != tail); > > /* >-- >2.43.7 > > Reviewed-by: Samiullah Khawaja