From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C015431F991 for ; Sun, 22 Mar 2026 09:24:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774171487; cv=none; b=Cz/ySdF0VZhs2gFZsukEl4c/ngnBSi9PpyU/OSu9PTBHc1DZFGp0tuYGv6WsyuXlCLNMOHbiv/Yk0UYLvvgQuTvzLBZP2cvQEvDDdzxU6M3gxcWJglzNSxfo7NEvN2F4ljmPzIcwmDYbiYJfXrION3WOpRvqbwh/WjYWp9IFia4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774171487; c=relaxed/simple; bh=n4C3ynhE7jxIrWpriieMpCCDCiYTKr9NecF5HXEHwPw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=RYThl4wZVytkubxpb6ZkAApVUmbrj4dv32xRqjanFn5f6MWo5QKuJIoDF6sGHQJS/cufUZOswN6HRiCSFbULZytFyJYwmtD+Y4qIWILMNCIAtvfBPRgvQzMg6B8vrxk6csUG0aTFoP7UPaSMnTR6Q9OTTLqy7bDNDWSe+SrDVxU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=FB5cQ62A; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="FB5cQ62A" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-486fb990b9eso87805e9.0 for ; Sun, 22 Mar 2026 02:24:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1774171483; x=1774776283; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=GplwjQbx6bBy+YNbaPGexypRaWChzbTAh68wSARB7Z8=; b=FB5cQ62AaEYQrr+TVBg2UEVXq8o6EQRan1/8+zEnLHQMWaksnrXwL8LxLi4JYI1ExG NO2jyVqT8DGj1JB8I8WIpB4SNhyY4LPq9gfpfK6rPPlJxwIT0QTX/Bknq02HqWRoyW7K 6tC6BdcaONCmi9wAZ3Yv4GhoY+hUkXbpyW4o9Zy7czwlOxJnV4rjnxHeP26siFrudQp8 M+Y1Wh7Oc4hWOAo+Y+/k05cnMYylvwBxrkIKWkkH9f1eV8swLlR9nkI6c/11i/Gr7BN5 SIx/RpGNBMXzrfhRVXhdMty2XLglr/eKa6MYskXkOB2+D14yGJOPsj+Dnj4QMM9i4nnF 0XNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774171483; x=1774776283; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-gg:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GplwjQbx6bBy+YNbaPGexypRaWChzbTAh68wSARB7Z8=; b=pdW4X2yaLv6rIVNl0qDq8yzqz0k/Sq+NsvAfTpm/zZWAdvj8/sLtI7roj++h3363nw rpnUmD8E2Y937bRZqlp9Ye5hq7xNgBgF2eh8jgDtvG8Gs29Yqs8Qsm0ydHscjSxCzmHo ZY5NYYSAz9SdUVgNLIs8FbxlCjXIUwcB1a+a4CyX5NuGFKKEYRsHe/Ldb4YOZn9JuElm ExPDOnvhmIScKz/SCLhgfSmeYJFZc11kEU81++zCSxLAHbKJfjEQ0x+mfpavjG2LkuMi LfWI8RFHeNstU2BT+O6kuFLeKoPImt/MQavZidnNlf+ExMViDxB/IlYsgNWrMea+Pn5e 8jAg== X-Gm-Message-State: AOJu0YzvEZboUdHO6eyCWXikVp6UKbg6RoaYe7GgPJW6FaRBqwBdkblG d9e085TadGT+nNrJWOYyXNDz6kfX8p4AslKfc8x90otoQSBklYs/KNRfhfFvf66bzQ== X-Gm-Gg: ATEYQzza2YCtOm2Wk844cOYbXQouuHH61Un9qIfWBcvn0uBUV9rWQUxuXoVCgK59UGK o2XkBhOnfEe+cebL9vADixAlTehnwPreiplBX4La1QGAjwQQqjP1B2zSY4a08BjTSBcF7RwAukz 33XaPQSICEMUfl8D6fm+zOFEwzSszC6nnOh0ikNkeTKHMJ6GaPp0miSOt/18oZnfDc6bPtjHvKD m8686ZcjTfIWzpw1DCCyUy8Qhdjp2WE4jG3bKzj9EkbuWIio3gYj8VPlr8uCacRD1TFACBcHMw6 zUqv9W2L3EwgV+EGrNqAqYakAJxLJc044ixD7MS6uR/hyGIDSyjIuI3pDsTf3LH+tsdOLZ6pJF7 3kgaNkY86qHnQB9ChhfwveSFoDEqNl8H28ivwQ302nuHCpjzlbESxbWydVZaex7bJ/bjQe7pQCY bE8M6J5ZvyiSEU/ihs8GFAgIFKCi/zxi0lYUS+nMEnTuQ8Gzgrw/WcAibxumWJhADFCkU= X-Received: by 2002:a05:600c:3f1b:b0:47e:dbb0:fbcd with SMTP id 5b1f17b1804b1-487034670bamr1436975e9.6.1774171482699; Sun, 22 Mar 2026 02:24:42 -0700 (PDT) Received: from google.com (54.95.38.34.bc.googleusercontent.com. [34.38.95.54]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b64703c27sm20799976f8f.18.2026.03.22.02.24.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2026 02:24:41 -0700 (PDT) Date: Sun, 22 Mar 2026 09:24:37 +0000 From: Mostafa Saleh To: Jacob Pan Cc: linux-kernel@vger.kernel.org, "iommu@lists.linux.dev" , Jason Gunthorpe , Alex Williamson , Joerg Roedel , David Matlack , Robin Murphy , Nicolin Chen , "Tian, Kevin" , Yi Liu , skhawaja@google.com, pasha.tatashin@soleen.com, Will Deacon , Baolu Lu Subject: Re: [PATCH V2 01/11] iommufd: Support a HWPT without an iommu driver for noiommu Message-ID: References: <20260312155637.376854-1-jacob.pan@linux.microsoft.com> <20260312155637.376854-2-jacob.pan@linux.microsoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260312155637.376854-2-jacob.pan@linux.microsoft.com> On Thu, Mar 12, 2026 at 08:56:27AM -0700, Jacob Pan wrote: > From: Jason Gunthorpe > > Create just a little part of a real iommu driver, enough to > slot in under the dev_iommu_ops() and allow iommufd to call > domain_alloc_paging_flags() and fail everything else. > > This allows explicitly creating a HWPT under an IOAS. > > Signed-off-by: Jason Gunthorpe > Signed-off-by: Jacob Pan > --- > drivers/iommu/iommufd/Makefile | 1 + > drivers/iommu/iommufd/hw_pagetable.c | 11 ++- > drivers/iommu/iommufd/hwpt_noiommu.c | 91 +++++++++++++++++++++++++ > drivers/iommu/iommufd/iommufd_private.h | 2 + > 4 files changed, 103 insertions(+), 2 deletions(-) > create mode 100644 drivers/iommu/iommufd/hwpt_noiommu.c > > diff --git a/drivers/iommu/iommufd/Makefile b/drivers/iommu/iommufd/Makefile > index 71d692c9a8f4..2b1a020b14a6 100644 > --- a/drivers/iommu/iommufd/Makefile > +++ b/drivers/iommu/iommufd/Makefile > @@ -10,6 +10,7 @@ iommufd-y := \ > vfio_compat.o \ > viommu.o > > +iommufd-$(CONFIG_VFIO_NOIOMMU) += hwpt_noiommu.o > iommufd-$(CONFIG_IOMMUFD_TEST) += selftest.o > > obj-$(CONFIG_IOMMUFD) += iommufd.o > diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/hw_pagetable.c > index fe789c2dc0c9..37316d77277d 100644 > --- a/drivers/iommu/iommufd/hw_pagetable.c > +++ b/drivers/iommu/iommufd/hw_pagetable.c > @@ -8,6 +8,13 @@ > #include "../iommu-priv.h" > #include "iommufd_private.h" > > +static const struct iommu_ops *get_iommu_ops(struct iommufd_device *idev) > +{ > + if (IS_ENABLED(CONFIG_VFIO_NOIOMMU) && !idev->igroup->group) > + return &iommufd_noiommu_ops; > + return dev_iommu_ops(idev->dev); > +} > + > static void __iommufd_hwpt_destroy(struct iommufd_hw_pagetable *hwpt) > { > if (hwpt->domain) > @@ -114,7 +121,7 @@ iommufd_hwpt_paging_alloc(struct iommufd_ctx *ictx, struct iommufd_ioas *ioas, > IOMMU_HWPT_ALLOC_DIRTY_TRACKING | > IOMMU_HWPT_FAULT_ID_VALID | > IOMMU_HWPT_ALLOC_PASID; > - const struct iommu_ops *ops = dev_iommu_ops(idev->dev); > + const struct iommu_ops *ops = get_iommu_ops(idev); > struct iommufd_hwpt_paging *hwpt_paging; > struct iommufd_hw_pagetable *hwpt; > int rc; > @@ -229,7 +236,7 @@ iommufd_hwpt_nested_alloc(struct iommufd_ctx *ictx, > struct iommufd_device *idev, u32 flags, > const struct iommu_user_data *user_data) > { > - const struct iommu_ops *ops = dev_iommu_ops(idev->dev); > + const struct iommu_ops *ops = get_iommu_ops(idev); > struct iommufd_hwpt_nested *hwpt_nested; > struct iommufd_hw_pagetable *hwpt; > int rc; > diff --git a/drivers/iommu/iommufd/hwpt_noiommu.c b/drivers/iommu/iommufd/hwpt_noiommu.c > new file mode 100644 > index 000000000000..0aa99f581ca3 > --- /dev/null > +++ b/drivers/iommu/iommufd/hwpt_noiommu.c > @@ -0,0 +1,91 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES > + */ > +#include > +#include > +#include "iommufd_private.h" > + > +static const struct iommu_domain_ops noiommu_amdv1_ops; > + > +struct noiommu_domain { > + union { > + struct iommu_domain domain; > + struct pt_iommu_amdv1 amdv1; > + }; > + spinlock_t lock; > +}; > +PT_IOMMU_CHECK_DOMAIN(struct noiommu_domain, amdv1.iommu, domain); > + > +static void noiommu_change_top(struct pt_iommu *iommu_table, > + phys_addr_t top_paddr, unsigned int top_level) > +{ > +} > + > +static spinlock_t *noiommu_get_top_lock(struct pt_iommu *iommupt) > +{ > + struct noiommu_domain *domain = > + container_of(iommupt, struct noiommu_domain, amdv1.iommu); > + > + return &domain->lock; > +} > + > +static const struct pt_iommu_driver_ops noiommu_driver_ops = { > + .get_top_lock = noiommu_get_top_lock, > + .change_top = noiommu_change_top, > +}; > + > +static struct iommu_domain * > +noiommu_alloc_paging_flags(struct device *dev, u32 flags, > + const struct iommu_user_data *user_data) > +{ > + struct pt_iommu_amdv1_cfg cfg = {}; > + struct noiommu_domain *dom; > + int rc; > + > + if (flags || user_data) > + return ERR_PTR(-EOPNOTSUPP); > + > + cfg.common.hw_max_vasz_lg2 = 64; > + cfg.common.hw_max_oasz_lg2 = 52; > + cfg.starting_level = 2; > + cfg.common.features = > + (BIT(PT_FEAT_DYNAMIC_TOP) | BIT(PT_FEAT_AMDV1_ENCRYPT_TABLES) | > + BIT(PT_FEAT_AMDV1_FORCE_COHERENCE)); > + > + dom = kzalloc(sizeof(*dom), GFP_KERNEL); > + if (!dom) > + return ERR_PTR(-ENOMEM); > + > + spin_lock_init(&dom->lock); > + dom->amdv1.iommu.nid = NUMA_NO_NODE; > + dom->amdv1.iommu.driver_ops = &noiommu_driver_ops; > + dom->domain.ops = &noiommu_amdv1_ops; > + > + /* Use mock page table which is based on AMDV1 */ > + rc = pt_iommu_amdv1_init(&dom->amdv1, &cfg, GFP_KERNEL); > + if (rc) { > + kfree(dom); > + return ERR_PTR(rc); > + } > + > + return &dom->domain; > +} > + > +static void noiommu_domain_free(struct iommu_domain *iommu_domain) > +{ > + struct noiommu_domain *domain = > + container_of(iommu_domain, struct noiommu_domain, domain); > + > + pt_iommu_deinit(&domain->amdv1.iommu); > + kfree(domain); > +} > + > +static const struct iommu_domain_ops noiommu_amdv1_ops = { > + IOMMU_PT_DOMAIN_OPS(amdv1), I see the appeal of re-using an existing page table implementation to keep track of iovas which -as far as I understand- are used as tokens for DMA pinned pages later, but maybe at least add some paragraph about that, as it is not immediately clear and that's a different design from the legacy noiommu VFIO code. Thanks, Mostafa > + .free = noiommu_domain_free, > +}; > + > +struct iommu_ops iommufd_noiommu_ops = { > + .domain_alloc_paging_flags = noiommu_alloc_paging_flags, > +}; > diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommufd/iommufd_private.h > index 6ac1965199e9..9c18c5eb1899 100644 > --- a/drivers/iommu/iommufd/iommufd_private.h > +++ b/drivers/iommu/iommufd/iommufd_private.h > @@ -464,6 +464,8 @@ static inline void iommufd_hw_pagetable_put(struct iommufd_ctx *ictx, > refcount_dec(&hwpt->obj.users); > } > > +extern struct iommu_ops iommufd_noiommu_ops; > + > struct iommufd_attach; > > struct iommufd_group { > -- > 2.34.1 >