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Mon, 26 May 2025 17:51:45 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E564F40056; Mon, 26 May 2025 17:50:19 +0200 (CEST) Received: from Webmail-eu.st.com (eqndag1node5.st.com [10.75.129.134]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9BE99ACB869; Mon, 26 May 2025 17:48:33 +0200 (CEST) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE5.st.com (10.75.129.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 26 May 2025 17:48:33 +0200 Received: from [10.48.86.222] (10.48.86.222) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 26 May 2025 17:48:32 +0200 Message-ID: Date: Mon, 26 May 2025 17:48:31 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] iio: adc: stm32-adc: Fix race in installing chained IRQ handler To: Jonathan Cameron , =?UTF-8?Q?Nuno_S=C3=A1?= CC: Chen Ni , , , , , , , , , , , , , , Olivier Moysan References: <20250515083101.3811350-1-nichen@iscas.ac.cn> <229cf78caaa7e9f2bb4cfa62c019acd51a1cd684.camel@gmail.com> <20250525120703.5dd89fc2@jic23-huawei> Content-Language: en-US From: Fabrice Gasnier In-Reply-To: <20250525120703.5dd89fc2@jic23-huawei> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-26_08,2025-05-26_02,2025-03-28_01 On 5/25/25 13:07, Jonathan Cameron wrote: > On Thu, 15 May 2025 11:26:56 +0100 > Nuno Sá wrote: > >> On Thu, 2025-05-15 at 16:31 +0800, Chen Ni wrote: >>> Fix a race where a pending interrupt could be received and the handler >>> called before the handler's data has been setup, by converting to >>> irq_set_chained_handler_and_data(). >>> >>> Fixes: d58c67d1d851 ("iio: adc: stm32-adc: add support for STM32MP1") >>> Signed-off-by: Chen Ni >>> --- >> >> Reviewed-by: Nuno Sá > Looks good to me and I've queued it up for after rc1. If any > ST folk have time to take a look that would be great. Hi Jonathan, One minor comment at my end, not sure if that changes a lot... This could be a fix for the older commit: 1add69880240 ("iio: adc: Add support for STM32 ADC core") Apart from that, you can add my: Tested-by: Fabrice Gasnier Reviewed-by: Fabrice Gasnier BR, Fabrice > > Jonathan > >> >>> Changelog: >>> >>> v1 -> v2: >>> >>> 1. Add Fixes tag. >>> --- >>>  drivers/iio/adc/stm32-adc-core.c | 7 +++---- >>>  1 file changed, 3 insertions(+), 4 deletions(-) >>> >>> diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc- >>> core.c >>> index bd3458965bff..21c04a98b3b6 100644 >>> --- a/drivers/iio/adc/stm32-adc-core.c >>> +++ b/drivers/iio/adc/stm32-adc-core.c >>> @@ -430,10 +430,9 @@ static int stm32_adc_irq_probe(struct platform_device >>> *pdev, >>>   return -ENOMEM; >>>   } >>>   >>> - for (i = 0; i < priv->cfg->num_irqs; i++) { >>> - irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); >>> - irq_set_handler_data(priv->irq[i], priv); >>> - } >>> + for (i = 0; i < priv->cfg->num_irqs; i++) >>> + irq_set_chained_handler_and_data(priv->irq[i], >>> + stm32_adc_irq_handler, >>> priv); >>>   >>>   return 0; >>>  } >