From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E6C23B47DA for ; Tue, 10 Mar 2026 22:40:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773182448; cv=none; b=s/iuxRuoLgRWRg6zLLOgDsPOwJEV/YXeBW2yIA4fbM49bREXiU5rK14ywc74Tpz1ZnL+bebAKFHxrJ6uE0oeHoo/o2sDSXaqzTgy2MH4ctw1svgjg7esdSipWVMTesQ/2voeJA5oSANnBKUSmIrxZwQai762nqYyUxCXlkSMV4M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773182448; c=relaxed/simple; bh=QlagcG569iyDW36sOowUIidoIUFncYMFxFhPg9u2FMQ=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=KlW5rTXq+28kzP2VGSpdcc7ZXHbqoCeq42pLcOaasPVEFMH8044AAY4DLw6iPn69zNHLjbhPmL9z1s1MyL35tBl0Oj4tkJ/xuUldjuhLcphkt9V2GAD7wtJHfnz7e8u1UHtwBz8bkrGAp+Jymti1YOo5I7GAkONhdH25NMhxI28= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=G/BdD7WU; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="G/BdD7WU" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-35845fcf0f5so430742a91.0 for ; Tue, 10 Mar 2026 15:40:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1773182446; x=1773787246; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=pPEOn0JI7dMVt6GUZj8Zs0LKFqW84f4XjO+buWlc6Sw=; b=G/BdD7WU2nuam2nzpEvElNRq4oYmicX5vUiLlR2hyd7aSo1JKNeVHWB22NVBRSinu9 /EPu6c/uZ3CzVXCrBn2VTNfqbPChxk3N7RmogXy/23CAqGqwuXvk+qX2ZI7iWPb76ubZ y8uehynxs8Iuu7Q5pzy3n++U4n4cLyXSR1HbnRP8Z5pE4dxnnhDCiyQ67v3/7wUfrY1u WGMGgSk1xSpFebTG56ESJHWghZBXYzcREq1Zh6QPAcYgc9WRI6akxcKo1AiAinzRFkMQ hv1fwFV5dSllB7ACZJO8BqPtu4svRcnnIunNV3bwvEqu6NHR0l3+6fPPPdaV4hWSWYK0 gyqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773182446; x=1773787246; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=pPEOn0JI7dMVt6GUZj8Zs0LKFqW84f4XjO+buWlc6Sw=; b=uQK3QfulwX5a4HCFkMVwuxxtcU4H0N75nPF8qOeCyamfgke3mmagrJG7umALBxtGCM b3j/pAxelA+0DivAD9ornfLyK47UTU5Bj3uB5uN2DmZWIKqFI6YKSxxHE0yAURNqZCuq S+VJ+mQ7BjYJSR3emxA5XQjoVlNkm4IUlI/hti4Zke53baitHPrUR+AKQleY4AC1p/H7 hnTrjN7mHONIO2uthCLfwsG+B18+VLdP784fYn/Sb6dilmriyDeWIBUlCq/CTM7vt2jm o9A3M+7vyxBow+VqLy0+2k7s8I1PugaTx5UieSZmYrHFmwApNb7WpGoUesK6sKbqPNWK d41w== X-Forwarded-Encrypted: i=1; AJvYcCX/w7Lt8ijFHhaTit/Vwmo1w+0mdJSK9FVw2s7ugw30rQDlZBRuyBfJxL3LH/l4rJdhOHAqayYkN80ko+U=@vger.kernel.org X-Gm-Message-State: AOJu0YySqMubajUA0mDE597o/Nc37PKh8xWlFnHxdpMkrC23njNwTi+g zw2ZgoWXfjHaLNJzsn2T3nJ9+gf6z/pL2RVhczC1Fvon6ug6UQNODVRJ59mhWerk39I3XCy3NAz HH8x4KQ== X-Received: from pjbiq4.prod.google.com ([2002:a17:90a:fb44:b0:359:92db:6c34]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:2e52:b0:359:f5f4:7740 with SMTP id 98e67ed59e1d1-35a02830179mr243315a91.17.1773182446399; Tue, 10 Mar 2026 15:40:46 -0700 (PDT) Date: Tue, 10 Mar 2026 15:40:44 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260203190711.458413-3-seanjc@google.com> <19935696-36cf-411b-af90-aabe6a98d7e7@amd.com> <947bf241-d149-4933-874a-de96aeb73dff@amd.com> <23ec6b06-96b9-42aa-937a-908b2ce73a69@amd.com> Message-ID: Subject: Re: [PATCH 2/2] KVM: SVM: Set/clear CR8 write interception when AVIC is (de)activated From: Sean Christopherson To: Tom Lendacky Cc: Naveen N Rao , Srikanth Aithal , Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , "Maciej S . Szmigiero" Content-Type: text/plain; charset="us-ascii" On Tue, Mar 10, 2026, Tom Lendacky wrote: > On 3/10/26 16:58, Sean Christopherson wrote: > > On Tue, Mar 10, 2026, Tom Lendacky wrote: > >> On 3/10/26 13:35, Sean Christopherson wrote: > >>> On Tue, Mar 10, 2026, Tom Lendacky wrote: > >>>> I'm just saying that the unconditional trap for CR8_WRITE isn't flawed > >>>> for SEV-ES+ because AVIC can't work with SEV, so there isn't any time > >>>> that CR8 writes shouldn't be trapped. > >>> > >>> Yeah, I forgot that (obviously). > >>> > >>> But sync_cr8_to_lapic() is very broken, no? INTERCEPT_CR8_WRITE will never be > >>> set, and svm->vmcb->control.int_ctl will become stale as soon as the VMSA is > >>> live, and so in all likelihood KVM is crushing CR8 to zero for SEV-ES guests. > >> > >> I don't think so. V_TPR is written on #VMEXIT even for SEV-ES+ guests, > >> and since it is a trap, CR8 is set and so V_TPR should have that value. > >> That would imply sync_cr8_to_lapic() should do the right thing. > > > > But isn't svm->vmcb->control.int_ctl stale? Oh. "control", not "save". /facepalm > > > > Ah, and I assume Secure AVIC hides vTPR from the host? Or at least prevents the > > host from setting it? > > Secure AVIC will prevent the host from setting it since the backing page > lives in guest memory and is encrypted/private. What about vmcb->control.int_ctl though? IIUC, that's the source of truth for the effective vTPR, not the value in the virtual APIC page. > >> After attempting to verify this behavior it turns out that writes to CR8 > >> (and CR2) are, in fact, not trapped, but the APM was not updated with > >> this information (I'll send a patch to remove that code). KVM's CR8 > >> value is, however, synced with the proper value through > >> sync_cr8_to_lapic() because V_TPR in the VMCB is updated on #VMEXIT. > > > > Oh. Huh. So doesn't that mean that supporting Windows (or any other guest that > > uses TPR to mask interrupts) as an SEV-ES guest is practically impossible? Because > > while KVM can observe and manipulate guest CR8, KVM won't be able to precisely > > detect when TPR drops below a pending IRQ. > > Could we do something with virtual interrupt support? Today KVM uses the > virtual interrupt control to detect when an IRQ window opens. We could > do something similar by setting up the virtual interrupt priority, > V_INTR_PRIO, at the level of the current TPR/CR8 level. When the TPR > drops, that would trigger a #VMEXIT and allow the pending IRQ to be > injected. Thoughts? Uh, yes, that would work? I was thinking we couldn't model the priority, but obviously that's not true. FWIW, my preference would be to not add support unless someone asks for it :-)