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From: Sean Christopherson <seanjc@google.com>
To: "Chang S. Bae" <chang.seok.bae@intel.com>
Cc: pbonzini@redhat.com, kvm@vger.kernel.org,
	linux-kernel@vger.kernel.org,  chao.gao@intel.com
Subject: Re: [PATCH v2 01/16] KVM: x86: Rename register accessors to be GPR-specific
Date: Tue, 10 Mar 2026 16:12:27 -0700	[thread overview]
Message-ID: <abClW229Q_LHobgX@google.com> (raw)
In-Reply-To: <31093743-97e2-42a7-a989-84704f25f40e@intel.com>

On Tue, Mar 10, 2026, Chang S. Bae wrote:
> On 3/9/2026 6:23 PM, Sean Christopherson wrote:
> > 
> > Oh, yikes, I didn't even see that this series is playing games with the register
> > indices.
> > 
> > Whatever we do, the changelog asbolutely needs to call out the real motiviation.
> 
> Given the discussion here, it looks so apparent the changelog is missing
> that detail. I'll ensure something like what you wrote here to the revision.
> 
> > I'll try to come back to this tomorrow with more complete thoughts and hopefully
> 
> Sure, you call it. I know you have a lot on your plate, so I hope you feel
> free to take your time. Thanks!
> 
> > E.g. passing in VCPU_REGS_RIP to kvm_gpr_read() will compile just fine, but will
> > read the wrong register on APX capable hardware.
> 
> Right, so new semantics likely need to be established. As responded before,
> one option would be separate them in structure:
> 
> diff --git a/arch/x86/include/asm/kvm_host.h
> b/arch/x86/include/asm/kvm_host.h
> index ff07c45e3c73..ff8a317be5cf 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -795,10 +795,14 @@ enum kvm_only_cpuid_leafs {
> 
>  struct kvm_vcpu_arch {
>         /*
> -        * rip and regs accesses must go through
> -        * kvm_{register,rip}_{read,write} functions.
> +        * regs accesses must go through kvm_register_{read,write}
> +        * functions.
>          */
>         unsigned long regs[NR_VCPU_REGS];
> +
> +       /* rip accesses must go through kvm_rip_{read,write} */
> +       unsigned long rip;

Ya, this is where I ended up too.  And then as prep work, we can and should
convert regs_{avail,dirty} to proper bitmaps so that the size can be dynamic
for 32-bit vs. 64-bit vs. APX-capable (or we could just use a "unsigned long",
it would only change what BUILD_BUG_ON()s are needed).

E.g. I have

        unsigned long regs[NR_VCPU_GENERAL_PURPOSE_REGS];
        unsigned long rip;
        DECLARE_BITMAP(regs_avail, NR_VCPU_TOTAL_REGS);
        DECLARE_BITMAP(regs_dirty, NR_VCPU_TOTAL_REGS);

and then the below as a final testing hack for APX.  I should be able to post a
small series later today, which will map out out most of the register crud (I
didn't do anything with the emulator, so it's not a complete prep series, but
it should be enough to allow us to choose a direction).

enum kvm_reg {
        VCPU_REGS_RAX = __VCPU_REGS_RAX,
        VCPU_REGS_RCX = __VCPU_REGS_RCX,
        VCPU_REGS_RDX = __VCPU_REGS_RDX,
        VCPU_REGS_RBX = __VCPU_REGS_RBX,
        VCPU_REGS_RSP = __VCPU_REGS_RSP,
        VCPU_REGS_RBP = __VCPU_REGS_RBP,
        VCPU_REGS_RSI = __VCPU_REGS_RSI,
        VCPU_REGS_RDI = __VCPU_REGS_RDI,
#ifdef CONFIG_X86_64
        VCPU_REGS_R8  = __VCPU_REGS_R8,
        VCPU_REGS_R9  = __VCPU_REGS_R9,
        VCPU_REGS_R10 = __VCPU_REGS_R10,
        VCPU_REGS_R11 = __VCPU_REGS_R11,
        VCPU_REGS_R12 = __VCPU_REGS_R12,
        VCPU_REGS_R13 = __VCPU_REGS_R13,
        VCPU_REGS_R14 = __VCPU_REGS_R14,
        VCPU_REGS_R15 = __VCPU_REGS_R15,
#define CONFIG_X86_APX

#endif

#ifdef CONFIG_X86_APX
        VCPU_REG_R16 = VCPU_REGS_R15 + 1,
        VCPU_REG_R17,
        VCPU_REG_R18,
        VCPU_REG_R19,
        VCPU_REG_R20,
        VCPU_REG_R21,
        VCPU_REG_R22,
        VCPU_REG_R23,
        VCPU_REG_R24,
        VCPU_REG_R25,
        VCPU_REG_R26,
        VCPU_REG_R27,
        VCPU_REG_R28,
        VCPU_REG_R29,
        VCPU_REG_R30,
        VCPU_REG_R31,
#endif
        NR_VCPU_GENERAL_PURPOSE_REGS,

        VCPU_REG_RIP = NR_VCPU_GENERAL_PURPOSE_REGS,

        VCPU_REG_PDPTR,
        VCPU_REG_CR0,
        /*
         * Alias AMD's ERAPS (not a real register) to CR3 so that common code
         * can trigger emulation of the RAP (Return Address Predictor) with
         * minimal support required in common code.  Piggyback CR3 as the RAP
         * is cleared on writes to CR3, i.e. marking CR3 dirty will naturally
         * mark ERAPS dirty as well.
         */
        VCPU_REG_CR3,
        VCPU_REG_ERAPS = VCPU_REG_CR3,
        VCPU_REG_CR4,
        VCPU_REG_RFLAGS,
        VCPU_REG_SEGMENTS,
        VCPU_REG_EXIT_INFO_1,
        VCPU_REG_EXIT_INFO_2,

        NR_VCPU_TOTAL_REGS,
};


  reply	other threads:[~2026-03-10 23:12 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-12 23:53 [PATCH v2 00/16] KVM: x86: Enable APX for guests Chang S. Bae
2026-01-12 23:53 ` [PATCH v2 01/16] KVM: x86: Rename register accessors to be GPR-specific Chang S. Bae
2026-03-05  1:35   ` Sean Christopherson
2026-03-07  1:32     ` Chang S. Bae
2026-03-09 23:28       ` Chang S. Bae
2026-03-10  1:23       ` Sean Christopherson
2026-03-10 22:05         ` Chang S. Bae
2026-03-10 23:12           ` Sean Christopherson [this message]
2026-01-12 23:53 ` [PATCH v2 02/16] KVM: x86: Refactor GPR accessors to differentiate register access types Chang S. Bae
2026-03-05  1:49   ` Sean Christopherson
2026-03-07  1:32     ` Chang S. Bae
2026-01-12 23:53 ` [PATCH v2 03/16] KVM: x86: Implement accessors for extended GPRs Chang S. Bae
2026-03-05  1:41   ` Sean Christopherson
2026-03-07  1:32     ` Chang S. Bae
2026-01-12 23:53 ` [PATCH v2 04/16] KVM: VMX: Introduce unified instruction info structure Chang S. Bae
2026-03-05  4:21   ` Sean Christopherson
2026-03-07  1:33     ` Chang S. Bae
2026-03-13  1:05       ` Sean Christopherson
2026-01-12 23:53 ` [PATCH v2 05/16] KVM: VMX: Refactor instruction information retrieval Chang S. Bae
2026-01-12 23:53 ` [PATCH v2 06/16] KVM: VMX: Refactor GPR index retrieval from exit qualification Chang S. Bae
2026-03-05  4:13   ` Sean Christopherson
2026-01-12 23:53 ` [PATCH v2 07/16] KVM: VMX: Support extended register index in exit handling Chang S. Bae
2026-01-12 23:54 ` [PATCH v2 08/16] KVM: nVMX: Propagate the extended instruction info field Chang S. Bae
2026-01-12 23:54 ` [PATCH v2 09/16] KVM: emulate: Support EGPR accessing and tracking Chang S. Bae
2026-03-05  4:22   ` Sean Christopherson
2026-01-12 23:54 ` [PATCH v2 10/16] KVM: emulate: Handle EGPR index and REX2-incompatible opcodes Chang S. Bae
2026-01-12 23:54 ` [PATCH v2 11/16] KVM: emulate: Support REX2-prefixed opcode decode Chang S. Bae
2026-01-12 23:54 ` [PATCH v2 12/16] KVM: emulate: Reject EVEX-prefixed instructions Chang S. Bae
2026-01-12 23:54 ` [PATCH v2 13/16] KVM: x86: Guard valid XCR0.APX settings Chang S. Bae
2026-01-12 23:54 ` [PATCH v2 14/16] KVM: x86: Expose APX foundational feature bit to guests Chang S. Bae
2026-01-19  5:55   ` Xiaoyao Li
2026-01-20 18:07     ` Edgecombe, Rick P
2026-01-20 20:50       ` Chang S. Bae
2026-01-21 19:59         ` Edgecombe, Rick P
2026-01-12 23:54 ` [PATCH v2 15/16] KVM: x86: Expose APX sub-features " Chang S. Bae
2026-01-12 23:54 ` [PATCH v2 16/16] KVM: x86: selftests: Add APX state handling and XCR0 sanity checks Chang S. Bae
2026-03-05  4:28   ` Sean Christopherson
2026-03-07  1:33     ` Chang S. Bae
2026-03-11 18:42       ` Paolo Bonzini

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