[PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Pengyu Luo]

From: White Lewis <liu224806@gmail.com>

The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
byte_intf_clk, the rate-change propagates through the divider up to the
parent PLL (byte_clk_src), halving the byte clock rate.

A simiar issue had been also encountered on SM8750.
b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").

Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
so that clk_set_rate() on the divider adjusts only the divider ratio,
leaving the parent PLL untouched.

Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
Signed-off-by: White Lewis <liu224806@gmail.com>
[pengyu: reword]
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
---
 drivers/clk/qcom/dispcc-sc8280xp.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c
index 5903a759d..e91dfed0f 100644
--- a/drivers/clk/qcom/dispcc-sc8280xp.c
+++ b/drivers/clk/qcom/dispcc-sc8280xp.c
@@ -1160,7 +1160,6 @@ static struct clk_regmap_div disp0_cc_mdss_byte0_div_clk_src = {
 			&disp0_cc_mdss_byte0_clk_src.clkr.hw,
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_regmap_div_ops,
 	},
 };
@@ -1175,7 +1174,6 @@ static struct clk_regmap_div disp1_cc_mdss_byte0_div_clk_src = {
 			&disp1_cc_mdss_byte0_clk_src.clkr.hw,
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_regmap_div_ops,
 	},
 };
@@ -1190,7 +1188,6 @@ static struct clk_regmap_div disp0_cc_mdss_byte1_div_clk_src = {
 			&disp0_cc_mdss_byte1_clk_src.clkr.hw,
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_regmap_div_ops,
 	},
 };
@@ -1205,7 +1202,6 @@ static struct clk_regmap_div disp1_cc_mdss_byte1_div_clk_src = {
 			&disp1_cc_mdss_byte1_clk_src.clkr.hw,
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_regmap_div_ops,
 	},
 };
-- 
2.53.0

Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Konrad Dybcio]

On 3/3/26 12:55 PM, Pengyu Luo wrote:
> From: White Lewis <liu224806@gmail.com>
> 
> The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
> had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
> byte_intf_clk, the rate-change propagates through the divider up to the
> parent PLL (byte_clk_src), halving the byte clock rate.
> 
> A simiar issue had been also encountered on SM8750.
> b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").
> 
> Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
> so that clk_set_rate() on the divider adjusts only the divider ratio,
> leaving the parent PLL untouched.
> 
> Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
> Signed-off-by: White Lewis <liu224806@gmail.com>
> [pengyu: reword]
> Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> ---

Looks like more platforms have this issue.. thanks for fixing this

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Dmitry Baryshkov]

On Tue, Mar 03, 2026 at 07:55:50PM +0800, Pengyu Luo wrote:
> From: White Lewis <liu224806@gmail.com>
> 
> The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
> had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
> byte_intf_clk, the rate-change propagates through the divider up to the
> parent PLL (byte_clk_src), halving the byte clock rate.
> 
> A simiar issue had been also encountered on SM8750.
> b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").
> 
> Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
> so that clk_set_rate() on the divider adjusts only the divider ratio,
> leaving the parent PLL untouched.
> 
> Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
> Signed-off-by: White Lewis <liu224806@gmail.com>
> [pengyu: reword]
> Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> ---
>  drivers/clk/qcom/dispcc-sc8280xp.c | 4 ----
>  1 file changed, 4 deletions(-)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Brian Masney]

Hi Pengyu and Konrad,

On Tue, Mar 03, 2026 at 01:10:43PM +0100, Konrad Dybcio wrote:
> On 3/3/26 12:55 PM, Pengyu Luo wrote:
> > From: White Lewis <liu224806@gmail.com>
> > 
> > The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
> > had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
> > byte_intf_clk, the rate-change propagates through the divider up to the
> > parent PLL (byte_clk_src), halving the byte clock rate.
> > 
> > A simiar issue had been also encountered on SM8750.
> > b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").
> > 
> > Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
> > so that clk_set_rate() on the divider adjusts only the divider ratio,
> > leaving the parent PLL untouched.
> > 
> > Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
> > Signed-off-by: White Lewis <liu224806@gmail.com>
> > [pengyu: reword]
> > Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> > ---
> 
> Looks like more platforms have this issue.. thanks for fixing this

I hope within the next week to post a new draft of my patch series to
keep certain clk rates intact when sibling and parent rate changes occur
[1]. This will be for certain critical clks, such as the ones used for
DRM and sound. I have it working with kunit, and just need to clean up
some of my new clk helpers and commit messages before I post a v5.

I'd like to test this on some real hardware and I have the Thinkpad x13s
with the sc8280xp SoC. Can this issue be reproduced on this hardware? If
so, can you provide me detailed instructions about how to trigger this
scenario?

[1] Latest public posting v4 from September
    https://lore.kernel.org/linux-clk/20250923-clk-tests-docs-v4-0-9205cb3d3cba@redhat.com/

Thanks,

Brian

Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Pengyu Luo]

On Wed, Mar 4, 2026 at 10:50 PM Brian Masney <bmasney@redhat.com> wrote:
>
> Hi Pengyu and Konrad,
>
> On Tue, Mar 03, 2026 at 01:10:43PM +0100, Konrad Dybcio wrote:
> > On 3/3/26 12:55 PM, Pengyu Luo wrote:
> > > From: White Lewis <liu224806@gmail.com>
> > >
> > > The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
> > > had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
> > > byte_intf_clk, the rate-change propagates through the divider up to the
> > > parent PLL (byte_clk_src), halving the byte clock rate.
> > >
> > > A simiar issue had been also encountered on SM8750.
> > > b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").
> > >
> > > Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
> > > so that clk_set_rate() on the divider adjusts only the divider ratio,
> > > leaving the parent PLL untouched.
> > >
> > > Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
> > > Signed-off-by: White Lewis <liu224806@gmail.com>
> > > [pengyu: reword]
> > > Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> > > ---
> >
> > Looks like more platforms have this issue.. thanks for fixing this
>
> I hope within the next week to post a new draft of my patch series to
> keep certain clk rates intact when sibling and parent rate changes occur
> [1]. This will be for certain critical clks, such as the ones used for
> DRM and sound. I have it working with kunit, and just need to clean up
> some of my new clk helpers and commit messages before I post a v5.
>
> I'd like to test this on some real hardware and I have the Thinkpad x13s
> with the sc8280xp SoC. Can this issue be reproduced on this hardware? If
> so, can you provide me detailed instructions about how to trigger this
> scenario?
>

Quick answer, no, x13s uses a edp panel, not dsi. This issue is
related to dsi clks.

Best wishes,
Pengyu

> [1] Latest public posting v4 from September
>     https://lore.kernel.org/linux-clk/20250923-clk-tests-docs-v4-0-9205cb3d3cba@redhat.com/
>
> Thanks,
>
> Brian
>

Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Brian Masney]

On Wed, Mar 4, 2026 at 10:08 AM Pengyu Luo <mitltlatltl@gmail.com> wrote:
> On Wed, Mar 4, 2026 at 10:50 PM Brian Masney <bmasney@redhat.com> wrote:
> > On Tue, Mar 03, 2026 at 01:10:43PM +0100, Konrad Dybcio wrote:
> > > On 3/3/26 12:55 PM, Pengyu Luo wrote:
> > > > From: White Lewis <liu224806@gmail.com>
> > > >
> > > > The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
> > > > had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
> > > > byte_intf_clk, the rate-change propagates through the divider up to the
> > > > parent PLL (byte_clk_src), halving the byte clock rate.
> > > >
> > > > A simiar issue had been also encountered on SM8750.
> > > > b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").
> > > >
> > > > Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
> > > > so that clk_set_rate() on the divider adjusts only the divider ratio,
> > > > leaving the parent PLL untouched.
> > > >
> > > > Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
> > > > Signed-off-by: White Lewis <liu224806@gmail.com>
> > > > [pengyu: reword]
> > > > Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> > > > ---
> > >
> > > Looks like more platforms have this issue.. thanks for fixing this
> >
> > I hope within the next week to post a new draft of my patch series to
> > keep certain clk rates intact when sibling and parent rate changes occur
> > [1]. This will be for certain critical clks, such as the ones used for
> > DRM and sound. I have it working with kunit, and just need to clean up
> > some of my new clk helpers and commit messages before I post a v5.
> >
> > I'd like to test this on some real hardware and I have the Thinkpad x13s
> > with the sc8280xp SoC. Can this issue be reproduced on this hardware? If
> > so, can you provide me detailed instructions about how to trigger this
> > scenario?
> >
>
> Quick answer, no, x13s uses a edp panel, not dsi. This issue is
> related to dsi clks.

I posted my latest clk scaling work in an attempt to address the
underlying issue here.

https://lore.kernel.org/linux-clk/20260306-clk-scaling-v5-0-d21b84ee6f27@redhat.com/T/#t

Feedback welcome!

Brian

Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Bjorn Andersson]

On Tue, 03 Mar 2026 19:55:50 +0800, Pengyu Luo wrote:
> The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
> had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
> byte_intf_clk, the rate-change propagates through the divider up to the
> parent PLL (byte_clk_src), halving the byte clock rate.
> 
> A simiar issue had been also encountered on SM8750.
> b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").
> 
> [...]

Applied, thanks!

[1/1] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers
      commit: 0b151a6307205eb867250985a910a88787cbf12e

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Brian Masney]

Hi Qualcomm Folks,

On Fri, Mar 06, 2026 at 06:27:20PM -0500, Brian Masney wrote:
> On Wed, Mar 4, 2026 at 10:08 AM Pengyu Luo <mitltlatltl@gmail.com> wrote:
> > On Wed, Mar 4, 2026 at 10:50 PM Brian Masney <bmasney@redhat.com> wrote:
> > > On Tue, Mar 03, 2026 at 01:10:43PM +0100, Konrad Dybcio wrote:
> > > > On 3/3/26 12:55 PM, Pengyu Luo wrote:
> > > > > From: White Lewis <liu224806@gmail.com>
> > > > >
> > > > > The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
> > > > > had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
> > > > > byte_intf_clk, the rate-change propagates through the divider up to the
> > > > > parent PLL (byte_clk_src), halving the byte clock rate.
> > > > >
> > > > > A simiar issue had been also encountered on SM8750.
> > > > > b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").
> > > > >
> > > > > Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
> > > > > so that clk_set_rate() on the divider adjusts only the divider ratio,
> > > > > leaving the parent PLL untouched.
> > > > >
> > > > > Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
> > > > > Signed-off-by: White Lewis <liu224806@gmail.com>
> > > > > [pengyu: reword]
> > > > > Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
> > > > > ---
> > > >
> > > > Looks like more platforms have this issue.. thanks for fixing this
> > >
> > > I hope within the next week to post a new draft of my patch series to
> > > keep certain clk rates intact when sibling and parent rate changes occur
> > > [1]. This will be for certain critical clks, such as the ones used for
> > > DRM and sound. I have it working with kunit, and just need to clean up
> > > some of my new clk helpers and commit messages before I post a v5.
> > >
> > > I'd like to test this on some real hardware and I have the Thinkpad x13s
> > > with the sc8280xp SoC. Can this issue be reproduced on this hardware? If
> > > so, can you provide me detailed instructions about how to trigger this
> > > scenario?
> > >
> >
> > Quick answer, no, x13s uses a edp panel, not dsi. This issue is
> > related to dsi clks.
> 
> I posted my latest clk scaling work in an attempt to address the
> underlying issue here.

Ignore my previous patch set. In my v6 that I just posted, I updated
clk-divider.c to support the new v2 clk negotiation logic. The
clk_regmap_div_ops uses this driver, so you shouldn't have to make any
code changes.

Anyways, would someone from Qualcomm be willing to test this? The
procedure is fairly simple:

1) Back out the patch:
   clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers
   (or one of the similar patches posted for other SoCs)

2) Apply my v6 series:
   clk: add support for v1 / v2 clock rate negotiation and kunit tests
   https://lore.kernel.org/linux-clk/20260313-clk-scaling-v6-0-ce89968c5247@redhat.com/T/#

3) Boot... everything should behave the same as prior to my patch set.
   The clk crash will still occur.

4) Reboot, and boot the kernel this time with the clk_v2_rate_negotiation
   kernel parameter to globally opt into the v2 negotiation logic. The clk crash
   hopefully shouldn't occur.

Thanks,

Brian

Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Konrad Dybcio]

On 3/13/26 5:54 PM, Brian Masney wrote:
> Hi Qualcomm Folks,
> 
> On Fri, Mar 06, 2026 at 06:27:20PM -0500, Brian Masney wrote:
>> On Wed, Mar 4, 2026 at 10:08 AM Pengyu Luo <mitltlatltl@gmail.com> wrote:
>>> On Wed, Mar 4, 2026 at 10:50 PM Brian Masney <bmasney@redhat.com> wrote:
>>>> On Tue, Mar 03, 2026 at 01:10:43PM +0100, Konrad Dybcio wrote:
>>>>> On 3/3/26 12:55 PM, Pengyu Luo wrote:

[...]

> Ignore my previous patch set. In my v6 that I just posted, I updated
> clk-divider.c to support the new v2 clk negotiation logic. The
> clk_regmap_div_ops uses this driver, so you shouldn't have to make any
> code changes.
> 
> Anyways, would someone from Qualcomm be willing to test this? The
> procedure is fairly simple:

Unfortunately, I don't think it's easy to get your hands on a 8280
device with DSI.. maybe Pengyu could test that on his tablet/laptop.

Konrad

Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

[Brian Masney]

Hi Konrad,

On Mon, Mar 23, 2026 at 8:48 AM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
> On 3/13/26 5:54 PM, Brian Masney wrote:
> > On Fri, Mar 06, 2026 at 06:27:20PM -0500, Brian Masney wrote:
> >> On Wed, Mar 4, 2026 at 10:08 AM Pengyu Luo <mitltlatltl@gmail.com> wrote:
> >>> On Wed, Mar 4, 2026 at 10:50 PM Brian Masney <bmasney@redhat.com> wrote:
> >>>> On Tue, Mar 03, 2026 at 01:10:43PM +0100, Konrad Dybcio wrote:
> >>>>> On 3/3/26 12:55 PM, Pengyu Luo wrote:
>
> [...]
>
> > Ignore my previous patch set. In my v6 that I just posted, I updated
> > clk-divider.c to support the new v2 clk negotiation logic. The
> > clk_regmap_div_ops uses this driver, so you shouldn't have to make any
> > code changes.
> >
> > Anyways, would someone from Qualcomm be willing to test this? The
> > procedure is fairly simple:
>
> Unfortunately, I don't think it's easy to get your hands on a 8280
> device with DSI.. maybe Pengyu could test that on his tablet/laptop.

It doesn't have to be an 8280 SoC. It could be any device that has the
issue where the parent rate change screws up that portion of the clock
tree, and crashes the device. This has been a long-standing issue in
the clk framework.  I know you recently posted a series for 5 other
SoCs with a similar change [1], so any of those other devices should
work as well.

[1] https://lore.kernel.org/linux-arm-msm/20260304-topic-dsi_byte_fixup-v1-0-b79b29f83176@oss.qualcomm.com/

The kunit tests in my clk scaling patch set demonstrate the issues
that I have worked on. For example, in my test scenario, I start with
a parent, and two children. The parent can do any rate. The two
children are simple dividers. This is the current behavior today:

        KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ);
        KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child1_clk), 24 * HZ_PER_MHZ);
        KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ);

        ret = clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ);

        /*
         * The last sibling rate change is the one that was successful, and
         * wins. The parent, and two children are all changed to 32 MHz.
         */
        KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 32 * HZ_PER_MHZ);
        KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 32 * HZ_PER_MHZ);
        KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 32 * HZ_PER_MHZ);

With my changes, the clk framework will land on 96 MHz for the parent,
and 24 MHz and 32 MHz for the two children.

Anyways, it would be great if someone from Qualcomm would be willing
to help me test my changes on real hardware. If it requires code
changes to a specific clk provider, then I'm willing to also do that
work if someone can test for me. Getting confirmation that this is
fixed on real hardware will help to land my series that will provide a
solution to this problem that has existing in the clk framework since
it was introduced over 12 years ago.

Thanks,

Brian