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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-89a65ce3924sm60581406d6.24.2026.03.13.09.54.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 09:54:41 -0700 (PDT) Date: Fri, 13 Mar 2026 12:54:39 -0400 From: Brian Masney To: Pengyu Luo , Konrad Dybcio , Bjorn Andersson Cc: Michael Turquette , Stephen Boyd , Konrad Dybcio , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, White Lewis Subject: Re: [PATCH] clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers Message-ID: References: <20260303115550.9279-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/2.2.14 (2025-02-20) Hi Qualcomm Folks, On Fri, Mar 06, 2026 at 06:27:20PM -0500, Brian Masney wrote: > On Wed, Mar 4, 2026 at 10:08 AM Pengyu Luo wrote: > > On Wed, Mar 4, 2026 at 10:50 PM Brian Masney wrote: > > > On Tue, Mar 03, 2026 at 01:10:43PM +0100, Konrad Dybcio wrote: > > > > On 3/3/26 12:55 PM, Pengyu Luo wrote: > > > > > From: White Lewis > > > > > > > > > > The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src) > > > > > had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on > > > > > byte_intf_clk, the rate-change propagates through the divider up to the > > > > > parent PLL (byte_clk_src), halving the byte clock rate. > > > > > > > > > > A simiar issue had been also encountered on SM8750. > > > > > b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent"). > > > > > > > > > > Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks > > > > > so that clk_set_rate() on the divider adjusts only the divider ratio, > > > > > leaving the parent PLL untouched. > > > > > > > > > > Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller") > > > > > Signed-off-by: White Lewis > > > > > [pengyu: reword] > > > > > Signed-off-by: Pengyu Luo > > > > > --- > > > > > > > > Looks like more platforms have this issue.. thanks for fixing this > > > > > > I hope within the next week to post a new draft of my patch series to > > > keep certain clk rates intact when sibling and parent rate changes occur > > > [1]. This will be for certain critical clks, such as the ones used for > > > DRM and sound. I have it working with kunit, and just need to clean up > > > some of my new clk helpers and commit messages before I post a v5. > > > > > > I'd like to test this on some real hardware and I have the Thinkpad x13s > > > with the sc8280xp SoC. Can this issue be reproduced on this hardware? If > > > so, can you provide me detailed instructions about how to trigger this > > > scenario? > > > > > > > Quick answer, no, x13s uses a edp panel, not dsi. This issue is > > related to dsi clks. > > I posted my latest clk scaling work in an attempt to address the > underlying issue here. Ignore my previous patch set. In my v6 that I just posted, I updated clk-divider.c to support the new v2 clk negotiation logic. The clk_regmap_div_ops uses this driver, so you shouldn't have to make any code changes. Anyways, would someone from Qualcomm be willing to test this? The procedure is fairly simple: 1) Back out the patch: clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers (or one of the similar patches posted for other SoCs) 2) Apply my v6 series: clk: add support for v1 / v2 clock rate negotiation and kunit tests https://lore.kernel.org/linux-clk/20260313-clk-scaling-v6-0-ce89968c5247@redhat.com/T/# 3) Boot... everything should behave the same as prior to my patch set. The clk crash will still occur. 4) Reboot, and boot the kernel this time with the clk_v2_rate_negotiation kernel parameter to globally opt into the v2 negotiation logic. The clk crash hopefully shouldn't occur. Thanks, Brian