From: Dinh Nguyen <dinguyen@kernel.org>
To: Thorsten Blum <thorsten.blum@linux.dev>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [RESEND PATCH] clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
Date: Fri, 8 Nov 2024 07:15:25 -0600 [thread overview]
Message-ID: <aba3bcb7-3144-49c7-8acd-added30bbfdd@kernel.org> (raw)
In-Reply-To: <20241026155304.159716-2-thorsten.blum@linux.dev>
On 10/26/24 10:53, Thorsten Blum wrote:
> Since readl() returns a u32, the local variable reg can also have the
> data type u32. Furthermore, divf and divq are derived from reg and can
> also be a u32.
>
> Since do_div() casts the divisor to u32 anyway, changing the data type
> of divq to u32 also removes the following Coccinelle/coccicheck warning
> reported by do_div.cocci:
>
> WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
>
> Compile-tested only.
>
> Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
> ---
> drivers/clk/socfpga/clk-pll-a10.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied, thanks!
Dinh
prev parent reply other threads:[~2024-11-08 13:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-26 15:53 [RESEND PATCH] clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate() Thorsten Blum
2024-11-08 13:15 ` Dinh Nguyen [this message]
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