* [RESEND PATCH] clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
@ 2024-10-26 15:53 Thorsten Blum
2024-11-08 13:15 ` Dinh Nguyen
0 siblings, 1 reply; 2+ messages in thread
From: Thorsten Blum @ 2024-10-26 15:53 UTC (permalink / raw)
To: Dinh Nguyen, Michael Turquette, Stephen Boyd
Cc: Thorsten Blum, linux-clk, linux-kernel
Since readl() returns a u32, the local variable reg can also have the
data type u32. Furthermore, divf and divq are derived from reg and can
also be a u32.
Since do_div() casts the divisor to u32 anyway, changing the data type
of divq to u32 also removes the following Coccinelle/coccicheck warning
reported by do_div.cocci:
WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
Compile-tested only.
Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
---
drivers/clk/socfpga/clk-pll-a10.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index b028f25c658a..62eed964c3d0 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -35,7 +35,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
- unsigned long divf, divq, reg;
+ u32 divf, divq, reg;
unsigned long long vco_freq;
/* read VCO1 reg for numerator and denominator */
--
2.47.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [RESEND PATCH] clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
2024-10-26 15:53 [RESEND PATCH] clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate() Thorsten Blum
@ 2024-11-08 13:15 ` Dinh Nguyen
0 siblings, 0 replies; 2+ messages in thread
From: Dinh Nguyen @ 2024-11-08 13:15 UTC (permalink / raw)
To: Thorsten Blum, Michael Turquette, Stephen Boyd; +Cc: linux-clk, linux-kernel
On 10/26/24 10:53, Thorsten Blum wrote:
> Since readl() returns a u32, the local variable reg can also have the
> data type u32. Furthermore, divf and divq are derived from reg and can
> also be a u32.
>
> Since do_div() casts the divisor to u32 anyway, changing the data type
> of divq to u32 also removes the following Coccinelle/coccicheck warning
> reported by do_div.cocci:
>
> WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
>
> Compile-tested only.
>
> Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
> ---
> drivers/clk/socfpga/clk-pll-a10.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied, thanks!
Dinh
^ permalink raw reply [flat|nested] 2+ messages in thread
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2024-10-26 15:53 [RESEND PATCH] clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate() Thorsten Blum
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