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([2a01:e0a:3d9:2080:3819:3250:4f73:db31]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a568b4c969sm13226726f8f.85.2025.06.17.02.36.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Jun 2025 02:36:36 -0700 (PDT) Message-ID: Date: Tue, 17 Jun 2025 11:36:36 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH 4/5] phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3588 variant To: michael.riesch@collabora.com, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Jagan Teki , Sebastian Reichel , Collabora Kernel Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org References: <20250616-rk3588-csi-dphy-v1-0-84eb3b2a736c@collabora.com> <20250616-rk3588-csi-dphy-v1-4-84eb3b2a736c@collabora.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20250616-rk3588-csi-dphy-v1-4-84eb3b2a736c@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 17/06/2025 10:54, Michael Riesch via B4 Relay wrote: > From: Michael Riesch > > The Rockchip RK3588 MIPI CSI-2 DPHY can be supported using the existing > phy-rockchip-inno-csidphy driver, the notable differences being > - the control bits in the GRF > - the additional reset line > Add support for this variant. > > Signed-off-by: Michael Riesch > --- > drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c > index 75533d071025..0840be668bfd 100644 > --- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c > +++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c > @@ -30,6 +30,8 @@ > #define RK3568_GRF_VI_CON0 0x0340 > #define RK3568_GRF_VI_CON1 0x0344 > > +#define RK3588_CSIDPHY_GRF_CON0 0x0000 > + > /* PHY */ > #define CSIDPHY_CTRL_LANE_ENABLE 0x00 > #define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6) > @@ -115,6 +117,12 @@ static const struct dphy_reg rk3568_grf_dphy_regs[] = { > [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3568_GRF_VI_CON0, 1, 8), > }; > > +static const struct dphy_reg rk3588_grf_dphy_regs[] = { > + [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 0), > + [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 4, 4), > + [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3588_CSIDPHY_GRF_CON0, 1, 8), > +}; > + > struct hsfreq_range { > u32 range_h; > u8 cfg_bit; > @@ -373,6 +381,15 @@ static const struct dphy_drv_data rk3568_mipidphy_drv_data = { > .grf_regs = rk3568_grf_dphy_regs, > }; > > +static const struct dphy_drv_data rk3588_mipidphy_drv_data = { > + .pwrctl_offset = -1, > + .ths_settle_offset = RK3568_CSIDPHY_CLK_WR_THS_SETTLE, > + .calib_offset = RK3568_CSIDPHY_CLK_CALIB_EN, > + .hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges, > + .num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges), > + .grf_regs = rk3588_grf_dphy_regs, > +}; > + > static const struct of_device_id rockchip_inno_csidphy_match_id[] = { > { > .compatible = "rockchip,px30-csi-dphy", > @@ -394,6 +411,10 @@ static const struct of_device_id rockchip_inno_csidphy_match_id[] = { > .compatible = "rockchip,rk3568-csi-dphy", > .data = &rk3568_mipidphy_drv_data, > }, > + { > + .compatible = "rockchip,rk3588-csi-dphy", > + .data = &rk3588_mipidphy_drv_data, > + }, > {} > }; > MODULE_DEVICE_TABLE(of, rockchip_inno_csidphy_match_id); > @@ -435,7 +456,7 @@ static int rockchip_inno_csidphy_probe(struct platform_device *pdev) > return PTR_ERR(priv->pclk); > } > > - priv->rst = devm_reset_control_get(dev, "apb"); > + priv->rst = devm_reset_control_array_get(dev, RESET_CONTROL_EXCLUSIVE); It would be preferable to have the names of the resets lines and use devm_reset_control_bulk_get_exclusive(), and probably add the reset names to dphy_drv_data Neil > if (IS_ERR(priv->rst)) { > dev_err(dev, "failed to get system reset control\n"); > return PTR_ERR(priv->rst); >