[PATCH v5 0/2] Add Loongson-2K0300 processor support

[PATCH v5 0/2] Add Loongson-2K0300 processor support

[wjjsn]

From: wjjsn <2858482031@qq.com>

The first patch adds the necessary DT binding documentation,
and the second patch adds the DTS and DTSI files for the SoC
and the board.

Changes in v5:
- Remove unneed properties clock-names in node clk

Changes in v4:
- Fix a typo in v3 dt-bindings where 'loongson,99pi' was 
  incorrectly used instead of 'loongson,ls2k0300-ref'.

Changes in v3:
- Corrected the compatible string in DT bindings from 'loongson,99pi' 
  to 'loongson,ls2k0300-ref' to match the board's formal name.

Changes in v2:
- Add DT bindings.
- Included the missing Documentation/devicetree/bindings/ modification.

wjjsn (2):
  dt-bindings: loongarch: Add Loongson-2K0300
  loongarch: boot: dts: Add Loongson-2K0300 support

 .../bindings/loongarch/loongson.yaml          |  4 +
 arch/loongarch/boot/dts/Makefile              |  2 +-
 .../boot/dts/loongson-2k0300-ref.dts          | 34 +++++++
 arch/loongarch/boot/dts/loongson-2k0300.dtsi  | 94 +++++++++++++++++++
 4 files changed, 133 insertions(+), 1 deletion(-)
 create mode 100644 arch/loongarch/boot/dts/loongson-2k0300-ref.dts
 create mode 100644 arch/loongarch/boot/dts/loongson-2k0300.dtsi

-- 
2.43.0

Re: [PATCH v5 0/2] Add Loongson-2K0300 processor support

[Yao Zi]

On Sun, Mar 22, 2026 at 03:13:14PM +0800, wjjsn wrote:
> From: wjjsn <2858482031@qq.com>
> 
> The first patch adds the necessary DT binding documentation,
> and the second patch adds the DTS and DTSI files for the SoC
> and the board.

Please note I'm working on basic drivers/devicetree for 2K0300
platform[1][2][3], though the series haven't been updated for some
time... I've re-written the pinctrl part, and will try to re-spin all of
them next weekend.

Also, previously Huacai expressed preference on delaying devicetree
changes until basic drivers are ready[4], so anyway we should probably
get driver patches merged first.

Regards,
Yao Zi

[1]: https://lore.kernel.org/all/20250523095408.25919-4-ziyao@disroot.org/
[2]: https://lore.kernel.org/all/20250811163749.47028-2-ziyao@disroot.org/
[3]: https://lore.kernel.org/all/20250816033327.11359-2-ziyao@disroot.org/
[4]: https://lore.kernel.org/all/CAAhV-H6EDEf3U6w5KY3R3HCAdAbqDefqpE3ktCQeQtFbDK2Ypg@mail.gmail.com/

Re: [PATCH v5 0/2] Add Loongson-2K0300 processor support

[Huacai Chen]

On Sun, Mar 22, 2026 at 8:36 PM Yao Zi <me@ziyao.cc> wrote:
>
> On Sun, Mar 22, 2026 at 03:13:14PM +0800, wjjsn wrote:
> > From: wjjsn <2858482031@qq.com>
> >
> > The first patch adds the necessary DT binding documentation,
> > and the second patch adds the DTS and DTSI files for the SoC
> > and the board.
>
> Please note I'm working on basic drivers/devicetree for 2K0300
> platform[1][2][3], though the series haven't been updated for some
> time... I've re-written the pinctrl part, and will try to re-spin all of
> them next weekend.
>
> Also, previously Huacai expressed preference on delaying devicetree
> changes until basic drivers are ready[4], so anyway we should probably
> get driver patches merged first.
Yes, I confirm that.

Huacai

>
> Regards,
> Yao Zi
>
> [1]: https://lore.kernel.org/all/20250523095408.25919-4-ziyao@disroot.org/
> [2]: https://lore.kernel.org/all/20250811163749.47028-2-ziyao@disroot.org/
> [3]: https://lore.kernel.org/all/20250816033327.11359-2-ziyao@disroot.org/
> [4]: https://lore.kernel.org/all/CAAhV-H6EDEf3U6w5KY3R3HCAdAbqDefqpE3ktCQeQtFbDK2Ypg@mail.gmail.com/
>

Re: [PATCH v5 0/2] Add Loongson-2K0300 processor support

[wjjsn]

On 3/22/26 21:15, Huacai Chen wrote:
> On Sun, Mar 22, 2026 at 8:36 PM Yao Zi <me@ziyao.cc> wrote:
>> Also, previously Huacai expressed preference on delaying devicetree
>> changes until basic drivers are ready[4], so anyway we should probably
>> get driver patches merged first.
> Yes, I confirm that.
> 
> Huacai
> 

Hi Huacai and Yao,

I noticed that:
1. The current clock driver in mainline has some problems.
   The pll_ddr is lower than the user_manual,the clk_apb_gate will
   turn off by kernel while booting,though 16100000.serial is using
2. eiointc support for 2k0300 is missing.

Is there any WIP (Work In Progress) tree I can follow?
I'm happy to help with the development or testing.

Re: [PATCH v5 0/2] Add Loongson-2K0300 processor support

[Yao Zi]

On Mon, Mar 23, 2026 at 12:33:31AM +0800, wjjsn wrote:
> On 3/22/26 21:15, Huacai Chen wrote:
> > On Sun, Mar 22, 2026 at 8:36 PM Yao Zi <me@ziyao.cc> wrote:
> > > Also, previously Huacai expressed preference on delaying devicetree
> > > changes until basic drivers are ready[4], so anyway we should probably
> > > get driver patches merged first.
> > Yes, I confirm that.
> > 
> > Huacai
> > 
> 
> Hi Huacai and Yao,
> 
> I noticed that:
> 1. The current clock driver in mainline has some problems.
>   The pll_ddr is lower than the user_manual,

I'm not sure what do you mean. Do you observe lower clock frequency of
pll_ddr than the frequency specified in TRM (1GHz)? And if so, how?

clk-loongson2 doesn't have the ability to reclock hardware, but only
read out the frequency. PLL frequencies are all up to the bootloader.
So as long as you could confirm the values returned by recalc_rate()
match the register settings, there's nothing wrong in the clock driver.

Reclocking functionality could be introduced later. But even with
reclocking code, I doubt whether the DDR clock could be reclocked
at runtime since it supplies the memory controller.

>   the clk_apb_gate will
>   turn off by kernel while booting,though 16100000.serial is using

This is unlikely an issue in the clock driver, but rather the consumer
is doing something wrong, though I haven't seen similar issues when
working on the clock driver.

Please try booting the kernel with clk_ignore_unused, and check
/sys/kernel/debug/clk/clk_summary to see whether the serial correctly
acquires the apb gate clock. If not, one (and the most possible) reason
is both clock-frequency and clocks properties are specified in its
devicetree node, where 8250 driver would ignore the latter.

> 2. eiointc support for 2k0300 is missing.

This is expected. IOCSRs found on 2K0300 have a quite different layout
than previous generations of Loongson SoCs, and EIOINTC is in fact a
device located in IOCSR addressing space. We need to come up with a
better way to model the IOCSRs in devicetree, and it hasn't been done
yet.

> Is there any WIP (Work In Progress) tree I can follow?
> I'm happy to help with the development or testing.

Sorry there isn't one for now. I'm currently out of my lab, and could
only get things updated this weekend. Sorry for the inconvenience.

Regards,
Yao Zi

Re: [PATCH v5 0/2] Add Loongson-2K0300 processor support

[wjjsn]

On 3/23/26 10:42, Yao Zi wrote:
> On Mon, Mar 23, 2026 at 12:33:31AM +0800, wjjsn wrote:
>> On 3/22/26 21:15, Huacai Chen wrote:
>> 1. The current clock driver in mainline has some problems.
>>    The pll_ddr is lower than the user_manual,
> 
> I'm not sure what do you mean. Do you observe lower clock frequency of
> pll_ddr than the frequency specified in TRM (1GHz)? And if so, how?
> 
> clk-loongson2 doesn't have the ability to reclock hardware, but only
> read out the frequency. PLL frequencies are all up to the bootloader.
> So as long as you could confirm the values returned by recalc_rate()
> match the register settings, there's nothing wrong in the clock driver.
> 
> Reclocking functionality could be introduced later. But even with
> reclocking code, I doubt whether the DDR clock could be reclocked
> at runtime since it supplies the memory controller.

I observed that 'clk_ddr_div' operates at 800MHz instead of the 1GHz 
specified in the manual, and 'clk_dev_div' operates at 100MHz instead of 
the 200MHz specified in the manual. However, you mentioned that these 
settings are determined by the bootloader, so everything now makes sense

>>    the clk_apb_gate will
>>    turn off by kernel while booting,though 16100000.serial is using
> 
> This is unlikely an issue in the clock driver, but rather the consumer
> is doing something wrong, though I haven't seen similar issues when
> working on the clock driver.
> 
> Please try booting the kernel with clk_ignore_unused, and check
> /sys/kernel/debug/clk/clk_summary to see whether the serial correctly
> acquires the apb gate clock. If not, one (and the most possible) reason
> is both clock-frequency and clocks properties are specified in its
> devicetree node, where 8250 driver would ignore the latter.
>

  When I use 'clocks = <&clk LS2K0300_CLK_DEV_DIV>;', the system log 
gets stuck at the message about closing unused clocks, and there are no 
further logs. It seems like the clock for the serial port is being 
closed. However, if I set the parameter to not close unused clocks as a 
startup parameter, the serial port can continue to be used. If I use 
'clocks = <&clk LS2K0300_CLK_APB_GATE>;', then the clock for the serial 
port is not closed and can start normally. I have not specified the 
clock frequency in the device tree

>> 2. eiointc support for 2k0300 is missing.
> 
> This is expected. IOCSRs found on 2K0300 have a quite different layout
> than previous generations of Loongson SoCs, and EIOINTC is in fact a
> device located in IOCSR addressing space. We need to come up with a
> better way to model the IOCSRs in devicetree, and it hasn't been done
> yet.
> 
>> Is there any WIP (Work In Progress) tree I can follow?
>> I'm happy to help with the development or testing.
> 
> Sorry there isn't one for now. I'm currently out of my lab, and could
> only get things updated this weekend. Sorry for the inconvenience.

Okay, if you have a public repository, please let me know. If I have 
time, I would be happy to help with testing

Regards,
wjjsn

Re: [PATCH v5 0/2] Add Loongson-2K0300 processor support

[wjjsn]

On 3/24/26 23:09, wjjsn wrote:
> On 3/23/26 10:42, Yao Zi wrote:
>> On Mon, Mar 23, 2026 at 12:33:31AM +0800, wjjsn wrote:
>>> On 3/22/26 21:15, Huacai Chen wrote:
>>> 1. The current clock driver in mainline has some problems.
>>>    The pll_ddr is lower than the user_manual,
>>

Sorry for the formatting issues and
the messed up attribution in my previous mail.

The statement
"1. The current clock driver in mainline has some problems..."
was actually my observation, not Huacai's.

Also, I apologize for the long lines;
I will fix my mail client's line-wrapping settings for future discussions.

Regards,
wjjsn

Re: [PATCH v5 0/2] Add Loongson-2K0300 processor support

[Yao Zi]

On Tue, Mar 24, 2026 at 11:09:16PM +0800, wjjsn wrote:
> On 3/23/26 10:42, Yao Zi wrote:
> > On Mon, Mar 23, 2026 at 12:33:31AM +0800, wjjsn wrote:

...

> > >    the clk_apb_gate will
> > >    turn off by kernel while booting,though 16100000.serial is using
> > 
> > This is unlikely an issue in the clock driver, but rather the consumer
> > is doing something wrong, though I haven't seen similar issues when
> > working on the clock driver.
> > 
> > Please try booting the kernel with clk_ignore_unused, and check
> > /sys/kernel/debug/clk/clk_summary to see whether the serial correctly
> > acquires the apb gate clock. If not, one (and the most possible) reason
> > is both clock-frequency and clocks properties are specified in its
> > devicetree node, where 8250 driver would ignore the latter.
> > 
> 
>  When I use 'clocks = <&clk LS2K0300_CLK_DEV_DIV>;', the system log gets
> stuck at the message about closing unused clocks, and there are no further
> logs. It seems like the clock for the serial port is being closed. However,
> if I set the parameter to not close unused clocks as a startup parameter,
> the serial port can continue to be used. If I use 'clocks = <&clk
> LS2K0300_CLK_APB_GATE>;', then the clock for the serial port is not closed
> and can start normally. I have not specified the clock frequency in the

This is the expected behavior, because LS2K0300_CLK_APB_GATE takes
LS2K0300_CLK_APB_DIV as parent, and unused clocks would be automatically
disabled by kernel.

It's intended to let consumers take the GATE clock instead of the DIV
clock, just like what you have done in your patch.

> Regards,
> wjjsn

Regards,
Yao Zi