From: Binbin Wu <binbin.wu@linux.intel.com>
To: Chao Gao <chao.gao@intel.com>
Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org,
x86@kernel.org, reinette.chatre@intel.com, ira.weiny@intel.com,
kai.huang@intel.com, dan.j.williams@intel.com,
yilun.xu@linux.intel.com, sagis@google.com,
vannapurve@google.com, paulmck@kernel.org, nik.borisov@suse.com,
Farrah Chen <farrah.chen@intel.com>,
"Kirill A. Shutemov" <kas@kernel.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [PATCH v2 11/21] x86/virt/seamldr: Allocate and populate a module update request
Date: Thu, 27 Nov 2025 16:39:16 +0800 [thread overview]
Message-ID: <ace280a8-e8cf-4eeb-a924-f88ec1f4ac67@linux.intel.com> (raw)
In-Reply-To: <a8073390-b952-43a1-8e63-18c2a10bb721@linux.intel.com>
On 11/27/2025 4:30 PM, Binbin Wu wrote:
>
>
> On 10/1/2025 10:52 AM, Chao Gao wrote:
> [...]
>> +
>> +/* Allocate and populate a seamldr_params */
>> +static struct seamldr_params *alloc_seamldr_params(const void *module, int module_size,
>> + const void *sig, int sig_size)
>> +{
>> + struct seamldr_params *params;
>> + const u8 *ptr;
>> + int i;
>> +
>> + BUILD_BUG_ON(sizeof(struct seamldr_params) != SZ_4K);
>> + if (module_size > SEAMLDR_MAX_NR_MODULE_4KB_PAGES * SZ_4K)
>> + return ERR_PTR(-EINVAL);
>> +
>> + if (!IS_ALIGNED(module_size, SZ_4K) || !IS_ALIGNED(sig_size, SZ_4K) ||
>> + !IS_ALIGNED((unsigned long)module, SZ_4K) ||
>> + !IS_ALIGNED((unsigned long)sig, SZ_4K))
>> + return ERR_PTR(-EINVAL);
>> +
>> + /* seamldr_params accepts one 4KB-page for sigstruct */
>> + if (sig_size != SZ_4K)
> According to the link [2] you provided above, it seems that the layout of
> tdx_blob as following:
> tdx_blob
> |- u16 version
> |- u16 checksum
> |- u32 offset_of_module --------------------------------------|
> |- u8 signature[8] |
> |- u32 len 8KB + (N * 4KB) |
> |- u32 resv1 |
> |- u64 resv2[509] |
> |- u8 data[] |
> |- _u64 sigstruct[256] //2KB sigstruct |
> |- _u64 reserved2[256] |
> |- _u64 reserved3[N*512] //4KB aligned, optional, N >=0 |
> |- _u8 module[] //<-----------------------------|
Sorry about the mess.
tdx_blob
|- u16 version
|- u16 checksum
|- u32 offset_of_module --------------------------------------|
|- u8 signature[8] |
|- u32 len 8KB + (N * 4KB) |
|- u32 resv1 |
|- u64 resv2[509] |
|- u8 data[] |
|- _u64 sigstruct[256] //2KB sigstruct |
|- _u64 reserved2[256] |
|- _u64 reserved3[N*512] //4KB aligned, optional, N >=0 |
|- _u8 module[] //<-----------------------------|
>
> If N is not 0 for reserved3, then the sig_size passed will not be 4KB.
>
>
next prev parent reply other threads:[~2025-11-27 8:39 UTC|newest]
Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-01 2:52 [PATCH v2 00/21] Runtime TDX Module update support Chao Gao
2025-10-01 2:52 ` [PATCH v2 01/21] x86/virt/tdx: Print SEAMCALL leaf numbers in decimal Chao Gao
2025-10-01 2:52 ` [PATCH v2 02/21] x86/virt/tdx: Use %# prefix for hex values in SEAMCALL error messages Chao Gao
2025-10-01 2:52 ` [PATCH v2 03/21] x86/virt/tdx: Move low level SEAMCALL helpers out of <asm/tdx.h> Chao Gao
2025-10-01 2:52 ` [PATCH v2 04/21] x86/virt/tdx: Prepare to support P-SEAMLDR SEAMCALLs Chao Gao
2025-11-21 7:53 ` Binbin Wu
2025-12-02 7:23 ` Chao Gao
2025-10-01 2:52 ` [PATCH v2 05/21] x86/virt/seamldr: Introduce a wrapper for " Chao Gao
2025-11-21 8:41 ` Binbin Wu
2025-10-01 2:52 ` [PATCH v2 06/21] x86/virt/seamldr: Retrieve P-SEAMLDR information Chao Gao
2025-10-01 2:52 ` [PATCH v2 07/21] coco/tdx-host: Expose P-SEAMLDR information via sysfs Chao Gao
2025-10-30 21:54 ` Sagi Shahar
2025-10-30 23:05 ` dan.j.williams
2025-10-31 14:31 ` Sagi Shahar
2025-10-01 2:52 ` [PATCH v2 08/21] coco/tdx-host: Implement FW_UPLOAD sysfs ABI for TDX Module updates Chao Gao
2025-11-24 7:49 ` Binbin Wu
2025-12-02 7:20 ` Chao Gao
2025-10-01 2:52 ` [PATCH v2 09/21] x86/virt/seamldr: Block TDX Module updates if any CPU is offline Chao Gao
2025-10-01 2:52 ` [PATCH v2 10/21] x86/virt/seamldr: Verify availability of slots for TDX Module updates Chao Gao
2025-10-01 2:52 ` [PATCH v2 11/21] x86/virt/seamldr: Allocate and populate a module update request Chao Gao
2025-11-27 8:30 ` Binbin Wu
2025-11-27 8:39 ` Binbin Wu [this message]
2025-12-02 7:03 ` Chao Gao
2025-10-01 2:52 ` [PATCH v2 12/21] x86/virt/seamldr: Introduce skeleton for TDX Module updates Chao Gao
2025-10-01 2:52 ` [PATCH v2 13/21] x86/virt/seamldr: Abort updates if errors occurred midway Chao Gao
2025-10-01 2:52 ` [PATCH v2 14/21] x86/virt/seamldr: Shut down the current TDX module Chao Gao
2025-12-03 2:24 ` Binbin Wu
2025-10-01 2:52 ` [PATCH v2 15/21] x86/virt/tdx: Reset software states after TDX module shutdown Chao Gao
2025-10-01 2:53 ` [PATCH v2 16/21] x86/virt/seamldr: Handle TDX Module update failures Chao Gao
2025-10-28 2:53 ` Chao Gao
2025-10-01 2:53 ` [PATCH v2 17/21] x86/virt/seamldr: Install a new TDX Module Chao Gao
2025-10-01 2:53 ` [PATCH v2 18/21] x86/virt/seamldr: Do TDX per-CPU initialization after updates Chao Gao
2025-10-01 2:53 ` [PATCH v2 19/21] x86/virt/tdx: Establish contexts for the new TDX Module Chao Gao
2025-12-03 3:49 ` Binbin Wu
2025-10-01 2:53 ` [PATCH v2 20/21] x86/virt/tdx: Update tdx_sysinfo and check features post-update Chao Gao
2025-12-03 7:41 ` Binbin Wu
2025-10-01 2:53 ` [PATCH v2 21/21] x86/virt/tdx: Enable TDX Module runtime updates Chao Gao
2025-10-14 15:32 ` [PATCH v2 00/21] Runtime TDX Module update support Vishal Annapurve
2025-10-15 8:54 ` Reshetova, Elena
2025-10-15 14:19 ` Vishal Annapurve
2025-10-16 6:48 ` Reshetova, Elena
2025-10-15 15:02 ` Dave Hansen
2025-10-16 6:46 ` Reshetova, Elena
2025-10-16 17:47 ` Vishal Annapurve
2025-10-17 10:08 ` Reshetova, Elena
2025-10-18 0:01 ` Vishal Annapurve
2025-10-21 13:42 ` Reshetova, Elena
2025-10-22 7:14 ` Chao Gao
2025-10-22 15:42 ` Vishal Annapurve
2025-10-23 20:31 ` Vishal Annapurve
2025-10-23 21:10 ` Dave Hansen
2025-10-23 22:00 ` Vishal Annapurve
2025-10-24 7:43 ` Chao Gao
2025-10-24 18:02 ` Dave Hansen
2025-10-24 19:40 ` dan.j.williams
2025-10-24 20:00 ` Sean Christopherson
2025-10-24 20:14 ` Dave Hansen
2025-10-24 21:09 ` Vishal Annapurve
2025-10-24 20:13 ` Dave Hansen
2025-10-24 21:12 ` dan.j.williams
2025-10-24 21:19 ` Dave Hansen
2025-10-25 0:54 ` Vishal Annapurve
2025-10-25 1:42 ` dan.j.williams
2025-10-25 11:55 ` Vishal Annapurve
2025-10-25 12:01 ` Vishal Annapurve
2025-10-26 21:30 ` dan.j.williams
2025-10-26 22:01 ` Vishal Annapurve
2025-10-27 18:53 ` dan.j.williams
2025-10-28 0:42 ` Vishal Annapurve
2025-10-28 2:13 ` dan.j.williams
2025-10-28 17:00 ` Erdem Aktas
2025-10-29 0:56 ` Sean Christopherson
2025-10-29 2:17 ` dan.j.williams
2025-10-29 13:48 ` Sean Christopherson
2025-10-30 17:01 ` Vishal Annapurve
2025-10-31 2:53 ` Chao Gao
2025-11-19 22:44 ` Sagi Shahar
2025-11-20 2:47 ` Chao Gao
2025-11-20 23:38 ` Sagi Shahar
2025-10-28 23:48 ` Vishal Annapurve
2025-10-28 20:29 ` dan.j.williams
2025-10-28 20:32 ` dan.j.williams
2025-10-31 16:55 ` Sagi Shahar
2025-10-31 17:57 ` Vishal Annapurve
2025-11-01 2:18 ` Chao Gao
2025-11-01 2:05 ` Chao Gao
2025-11-12 14:09 ` Chao Gao
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