Re: [PATCH v3 0/2] arm64: qcom: sm8550: add DDR, LLCC & L3 CPU bandwidth scaling

Aaron Kling
2026-03-10T20:31:21Z

On Tue, Mar 10, 2026 at 3:20 PM Krzysztof Kozlowski
<krzysztof.kozlowski@oss.qualcomm.com> wrote:
>
> On 10/03/2026 21:05, Aaron Kling wrote:
> >> ---
> >> Aaron Kling (2):
> >> dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
> >> arm64: dts: qcom: sm8550: add cpu OPP table with DDR, LLCC & L3 bandwidths
> >>
> >> .../bindings/interconnect/qcom,osm-l3.yaml | 1 +
> >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 367 +++++++++++++++++++++
> >> 2 files changed, 368 insertions(+)
> >> ---
> >> base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
> >> change-id: 20260207-sm8550-ddr-bw-scaling-b1524827f207
> >>
> >> Best regards,
> >> --
> >> Aaron Kling <webgeek1234@gmail.com>
> >
> > What is the normal merge sequence and window for linux-arm-msm? I see
> > several things that have been picked up for -next recently, but none
> > of my sm8550 patches that have been reviewed / approved have been
> > picked up yet.
>
>
> This one is probably waiting on interconnect, no? Not saying that
> merging here is easy, quite the opposite - it's frustrating, but you can
> help by responding with actual data, e.g. bindings were merged and DTS
> can go, instead of just content-less ping.

So patch 1, the bindings, has to go via a different tree; then patch 2
goes via linux-arm-msm? Or does the first patch need an ack from other
people? I was assuming both of these could be handled by the
linux-arm-msm maintainers.

Part of this was a reminder, yes, but the question is still honest. I
don't know what the expected merge window is here, knowing that is
good to know if something got lost in the mix. I've got a couple other
patches as well that are standalone dt changes with no other deps.
I've had patches to other subsystems that have sat for four or five
cycles just waiting on the subsystem maintainers.

Aaron