Re: i.MX8MP: Fix HDMI LCDIF FIFO underruns

Krzysztof Hałasa
2026-03-20T13:20:24Z

Maxime Ripard <mripard@kernel.org> writes:

>> > > - writel(FIELD_PREP(PANIC0_THRES_LOW_MASK, 1 * PANIC0_THRES_MAX / 3) |
>> > > - FIELD_PREP(PANIC0_THRES_HIGH_MASK, 2 * PANIC0_THRES_MAX / 3),
>> > > + writel(FIELD_PREP(PANIC0_THRES_LOW_MASK, DIV_ROUND_UP(1 * PANIC0_THRES_MAX, 3)) |
>> > > + FIELD_PREP(PANIC0_THRES_HIGH_MASK, DIV_ROUND_UP(2 * PANIC0_THRES_MAX, 3)),

> If this is related to the output resolution, the DT is the last place
> you should deal with this.

Well... just tested (v6.19 + patch) with 2160p30 and, surprise surprise,
it doesn't work for like 10% of the time. I.e., the display may freeze
at weston start and/or shutdown time, but otherwise works:

v6.19 (frozen screen while starting weston, same display, the patch
applied):
32FC6000: 2 2 2 2
32FC6010: 80000000 8700F00 12800B0 480008
32FC6020: A0058 1000007 0
32FC6030: 1 1
32FC6200: 8700F00 223C00 EF000000
32FC6210: 0 89000000 1
32FC6220: 0 0 0 0
32FC6230: 0 0 AB0155

OTOH NXP's 6.6.23 works all the time:
NCP v6.6.23 (a different i.MX8MP):
32FC6000: A A A A
32FC6010: 80000000 8700F00 12800B0 480008
32FC6020: A0058 10005 0
32FC6030: 1 1
32FC6200: 8700F00 A23C00 97C00000
32FC6210: 0 89000000 1
32FC6220: 0 0 0 0
32FC6230: 0 0 AB0155

32FC600x 2 vs. A is pixel clock inversion.
32FC6208 is config P_SIZE, T_SIZE + pitch.

More tests after weekend.
--
Krzysztof "Chris" Hałasa

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