From: "Christoph Lameter (Ampere)" <cl@linux.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: Yang Shi <yang@os.amperecomputing.com>,
will@kernel.org, anshuman.khandual@arm.com,
scott@os.amperecomputing.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [v2 PATCH] arm64: mm: force write fault for atomic RMW instructions
Date: Thu, 23 May 2024 12:43:34 -0700 (PDT) [thread overview]
Message-ID: <ad87bb77-a9a5-2c0d-b4b2-13db09615d7c@linux.com> (raw)
In-Reply-To: <Zk-SNVyEHT1UsxqD@arm.com>
On Thu, 23 May 2024, Catalin Marinas wrote:
>>> While this class includes all atomics that currently require write
>>> permission, there's some unallocated space in this range and we don't
>>> know what future architecture versions may introduce. Unfortunately we
>>> need to check each individual atomic op in this class (not sure what the
>>> overhead will be).
>>
>> Can you tell us which bits or pattern is not allocated? Maybe we can exclude
>> that from the pattern.
>
> Yes, it may be easier to exclude those patterns. See the Arm ARM K.a
> section C4.1.94.29 (page 791).
Hmmm. We could consult an exception table once the pattern matches to
reduce the overhead.
However, the harm done I think is acceptable even if we leave things as
is. In the worst case we create unnecesssary write fault processing for an
"atomic op" that does not need write access. Also: Why would it need to be
atomic if it does not write???
It is more likely that new atomic ops are added that require write
permissions. Those will then just work. Otherwise we would need to
maintain an exception table of unallocated instructions that would then
have to shrink depending on new atomics added.
The ultimate solution would be to change the spec so that arm processors
can skip useless read faults.
next prev parent reply other threads:[~2024-05-23 19:43 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-20 16:56 [v2 PATCH] arm64: mm: force write fault for atomic RMW instructions Yang Shi
2024-05-23 17:07 ` Catalin Marinas
2024-05-23 18:09 ` Christoph Lameter (Ampere)
2024-05-23 19:00 ` Catalin Marinas
2024-05-23 19:43 ` Christoph Lameter (Ampere) [this message]
2024-05-23 21:34 ` Catalin Marinas
2024-05-23 22:13 ` Yang Shi
2024-06-03 16:06 ` Catalin Marinas
2024-06-03 20:34 ` Yang Shi
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