From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 066F43537E4 for ; Wed, 15 Apr 2026 08:01:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776240076; cv=none; b=l3+lZCje+r4BpW7d8q2X8b+qR83u1w6uxaqexmt/Vf0Pk66YJx2flJ+z3oYuToFjoklK6ZhUim4ArC/ir2kAUWNRZooodnJdvYhwd+ZFFDGzlL2q/HFmysCyivKuPVccAOaT98qajZGXUpWHhkkcB3Td2Y7D1zbtvQMVdPAtFJw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776240076; c=relaxed/simple; bh=bNtpmVdUY7eXlqDgRXn771eFIU2Y0JM4GpZ5sO/yJhs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=WXi2P+DQx5fuO+3VxXEvawFE6nkiee9lvK8P2TmbRs+RF6/C6Ad9SJosWpS8eRIF4FV8MJnFKwVsOnJPcXpu6YMtwWvqzHMcfMVTOCjDDv3j9ZM6NF97b01dX5TP7Sf3B6zU4sQTuApN39yCgN8ZrIqZ8BNlsDxWKD8QYNc0Njo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=qRpE9OIt; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="qRpE9OIt" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 711CE4FAA; Wed, 15 Apr 2026 01:01:08 -0700 (PDT) Received: from e129823.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C7213F641; Wed, 15 Apr 2026 01:01:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776240074; bh=bNtpmVdUY7eXlqDgRXn771eFIU2Y0JM4GpZ5sO/yJhs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=qRpE9OItpeLeSnnq4zXep6wsvnxel7JhFtQ//Ye4qwq1pwNUa8NAGVXCBsMdV309d Ez/dM5OHBIJv6VGGs3b+OqOVs4cJTqsSRp8W8IqKNPamfoct8O6GBgT7zbvMvSRfcC GhVedSn3qlVoALxhwtqntBwkxkIMcyoK+e+iXleI= Date: Wed, 15 Apr 2026 09:01:09 +0100 From: Yeoreum Yun To: Leo Yan Cc: Jie Gan , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com Subject: Re: [PATCH v4 3/9] coresight: etm4x: fix leaked trace id Message-ID: References: <20260413142003.3549310-1-yeoreum.yun@arm.com> <20260413142003.3549310-4-yeoreum.yun@arm.com> <20260414163221.GG356832@e132581.arm.com> <81fdef8a-a60e-4d29-948d-c4a07e23dad9@oss.qualcomm.com> <20260415072933.GH356832@e132581.arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260415072933.GH356832@e132581.arm.com> Hi Leo, > On Wed, Apr 15, 2026 at 09:21:21AM +0800, Jie Gan wrote: > > [...] > > > > > > @@ -918,8 +918,10 @@ static int etm4_enable_sysfs(struct coresight_device *csdev, struct coresight_pa > > > > > cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); > > > > > if (cfg_hash) { > > > > > ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); > > > > > - if (ret) > > > > > + if (ret) { > > > > > + etm4_release_trace_id(drvdata); > > > > > > > > If so, even an ID is reserved for failures, and the ID map is big enough > > > > for each CPU, we don't need to worry memory leak or ID used out issue ? > > > > > > However, in theory, this could lead to an ID leak, > > > so it would be better to release it in error cases. > > > > What I am thinking is as SoCs continue to grow more complex with an > > increasing number of subsystems, trace IDs may be exhausted in the near > > future. (that's why we have dynamic trace ID allocation/release). > > Thanks for the input. > > I am wandering if we can use "dev->devt" as the trace ID. A device's > major/minor number is unique in kernel and dev_t is defined as u32: > > typedef u32 __kernel_dev_t; > > And we can consolidate this for both SYSFS and PERF modes. > When I see the CORESIGHT_TRACE_ID_MAX: /* architecturally we have 128 IDs some of which are reserved */ #define CORESIGHT_TRACE_IDS_MAX 128 I think this came from the hardware restriction for number of TRACE_IDs. In this case, clamping the device_id to trace_id seems more complex and reduce some performance perspective. -- Sincerely, Yeoreum Yun