From: Sean Christopherson <seanjc@google.com>
To: David Kaplan <David.Kaplan@amd.com>
Cc: Thomas Gleixner <tglx@kernel.org>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"x86@kernel.org" <x86@kernel.org>,
"H. Peter Anvin" <hpa@zytor.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] x86/fpu: Disable shstk if no CET_USER state
Date: Mon, 6 Apr 2026 08:32:24 -0700 [thread overview]
Message-ID: <adPSCGx59ds5Fi1F@google.com> (raw)
In-Reply-To: <DS7PR12MB82011D57EE82CDCD28A1B146945DA@DS7PR12MB8201.namprd12.prod.outlook.com>
On Mon, Apr 06, 2026, David Kaplan wrote:
> > From: Sean Christopherson <seanjc@google.com>
> > On Fri, Apr 03, 2026, David Kaplan wrote:
> > > > From: Kaplan, David
> > > > > > ---
> > > > > > arch/x86/kernel/fpu/xstate.c | 11 +++++++++++
> > > > > > 1 file changed, 11 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/x86/kernel/fpu/xstate.c
> > b/arch/x86/kernel/fpu/xstate.c
> > > > > > index 76153dfb58c9..188323442b4d 100644
> > > > > > --- a/arch/x86/kernel/fpu/xstate.c
> > > > > > +++ b/arch/x86/kernel/fpu/xstate.c
> > > > > > @@ -855,6 +855,17 @@ void __init fpu__init_system_xstate(unsigned
> > int
> > > > > legacy_size)
> > > > > > goto out_disable;
> > > > > > }
> > > > > >
> > > > > > + if (boot_cpu_has(X86_FEATURE_USER_SHSTK) &&
> > > > > > + !(fpu_kernel_cfg.max_features & XFEATURE_MASK_CET_USER)) {
> > > > > > + /*
> > > > > > + * The kernel relies on XSAVES/XRSTORS to context switch
> > shadow
> > > > > > + * stack state. If this isn't present, disable user shadow
> > > > > > + * stacks.
> > > > > > + */
> > > > > > + pr_err("x86/fpu: CET_USER not supported in xstate when CET is
> > > > > supported. Disabling shadow stacks.\n");
> > > > > > + setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK);
> > > > >
> > > > > Doesn't this apply to IBT as well? This code is also misplaced, as it needs
> > to
> > > > > live after at least this code:
> > > >
> > > > Good point, it likely does. I can't confirm that as I don't have IBT hardware,
> > > > but assuming that a guest can see CET_IBT=1 this same problem would
> > exist.
> > >
> > > Actually, I don't think this does apply to IBT as well. Per
> > > Documentation/arch/x86/shstk.rst, only kernel IBT is currently supported by
> > > Linux. And kernel IBT does not require either CET_USER or CET_KERNEL XSS
> > > support from what I see. (CET_KERNEL is only for the shadow stack related
> > > MSRs)
> >
> > KVM virtualizes IBT and SHSTK, for both user and kernel, and relies on the host
> > kernel to save/restore IA32_U_CET.
>
> I think you're talking about a nested virt scenario is that right?
FWIW, this isn't limited to running in a VM. Booting on bare metal with
e.g. noxsaves=1 would lead to the same problematic scenario.
> So KVM in L1 virtualizes IBT/SHSTK for L2 and relies on the L1 kernel to
> save/restore IA32_UCET? And the concern is that if L1 doesn't support the
> XSS components then this is broken.
>
> But it looks like kvm_setup_xss_caps() appears to check if host XSS includes
Gah, -ENOCOFFEE, I forgot that KVM manually verifies that the kernel will context
switch CET.
> all the CET components and will clear X86_FEATURE_SHSTK/IBT if they aren't
> present. So I think what you'd see is:
>
> L0: CPUID says SHSTK/IBT supported. XSS bits supported.
> L1: CPUID says SHSTK/IBT supported. XSS bits not supported
> L2: CPUID doesn't say SHSTK/IBT supported.
>
> Or did I misunderstand the scenario you're talking about?
next prev parent reply other threads:[~2026-04-06 15:32 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-03 15:49 [PATCH] x86/fpu: Disable shstk if no CET_USER state David Kaplan
2026-04-03 19:36 ` Sean Christopherson
2026-04-03 19:52 ` Kaplan, David
2026-04-03 20:10 ` Kaplan, David
2026-04-06 14:26 ` Sean Christopherson
2026-04-06 15:04 ` Kaplan, David
2026-04-06 15:32 ` Sean Christopherson [this message]
2026-04-07 21:30 ` Kaplan, David
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