From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F8E31514E4 for ; Mon, 6 Apr 2026 15:32:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775489547; cv=none; b=re7YJDZHmFESkKJPK8iWe7IfGqfbyG5mZUM/34KgTxJZOiDAxcTf3Q1DVeT0uevwkvY9ijLOkAFa2doJywx03UC4rteMwoDhDtRtLuM18gBmZ5tnnJLgdfCG2mK/0g38JgEilPJrzaKePQvEbmbar4TRqve4CXHx+pws0r+FWHs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775489547; c=relaxed/simple; bh=A7YFfjOgZ0dV5Qmbg9F4M8T4CSG5TMLCOuo6GjN5YqY=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=aSign+f3zU86xC6VFYqP/qx36vfhzDo6J6AOSH3VeaHdvtCj0JZk6SffvohITCqOP/zeaDGZXkphb7abpqr+0Bn+iGqQcperuDHOCxhCIg7kFpTlvyu/n8Z2nUmPiBZSXfAxfHnvenSl+cIRUl/Tv3qCxOM5BSV4A+Ur7YjyBC4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=gLBKviHt; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="gLBKviHt" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-358f058973fso4855237a91.1 for ; Mon, 06 Apr 2026 08:32:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1775489546; x=1776094346; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Uenen4DPO+TWBiiIQ43nG0mwCU4tRId5AjKnRqlND4o=; b=gLBKviHtfDblSPPctGesiPmiE5Z32XjsZGuZKldKfBJU/vq88mUeG9zaMymECt9rOl L73HjDgaa1Cxbb7oh72dJSyg+RRl7VFsNofR6cBVHlObfPjP7tHK8Hpm2EQ73PafFTsi CBEOOc3ODZE6HRB6HYPjMoRQyP7GsdGG5njVFIXq9lO/juy+DHU2HFwmljcg+kLmYZgL uFbYOvoWwcyIPXNuIRh4LtCT+IDb3cZDfDK6RL/tooy1O7QLDL8Lmf7eknYWUwLwHjWs JSM5rynSfq1Biu55O8D1SGfp4HsQ0XTWPQBSfV6WE563Nx8/pP5QdOLJkETMm0qluqb9 VnGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775489546; x=1776094346; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Uenen4DPO+TWBiiIQ43nG0mwCU4tRId5AjKnRqlND4o=; b=eWJvE5vPy4uYXqQ/B7IdkQZhdKHSRc49l3XpYwOwjpnQhqp5QjGOM9qkh9OTCJCnEk PVLyp3ZkjmEu/aqaVXMRwsaQFjdlXxdgfD0fUfOsRT8BX0h2hqYxZeICt2MPomjzX5YF 4H/zWnyib6EO1Ih+0cabIsQJbE6Sm4febM0GknAkgBUSrb+aVFjyjg8Bo2yLD06C1Qbp MilKVTXGaGbdzl4J7d1DoqDXCam456wqgEFptSBdjDnNtXrh+YzRHvgSIpIQx0q12sNu UTszn28OXGTQfRw8ZLMWPeGX1lVr4OnJrbKtE8WcsaPSEgVI2s1FdB3ecJkbOwyAJZ+r C+0A== X-Forwarded-Encrypted: i=1; AJvYcCU98NYwrM+MfJkqiOil49OofrEC7WZxCgi02bAqj2j5tc14cBLpGxNfTKlQUOHNWqOyrAlZjk6Z8ExJQn0=@vger.kernel.org X-Gm-Message-State: AOJu0YyNuJ1Lv1IdY7B7q0FpcbUTOnucrXxJMOA+mrmrN00TcV4OIbyB wm2e5wdpVeocsL3CElPc28ovvo00RnfTTqoQcfI7v3LbvBOHafuIJjfoeGSr+fzkGuFUv7l68nm v0/zPWg== X-Received: from pgbfy22.prod.google.com ([2002:a05:6a02:2a96:b0:c6d:caaa:3364]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:7d9d:b0:39b:e789:7d0b with SMTP id adf61e73a8af0-39f2f174eb5mr13336780637.52.1775489545558; Mon, 06 Apr 2026 08:32:25 -0700 (PDT) Date: Mon, 6 Apr 2026 08:32:24 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260403154915.2285621-1-david.kaplan@amd.com> Message-ID: Subject: Re: [PATCH] x86/fpu: Disable shstk if no CET_USER state From: Sean Christopherson To: David Kaplan Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "x86@kernel.org" , "H. Peter Anvin" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="us-ascii" On Mon, Apr 06, 2026, David Kaplan wrote: > > From: Sean Christopherson > > On Fri, Apr 03, 2026, David Kaplan wrote: > > > > From: Kaplan, David > > > > > > --- > > > > > > arch/x86/kernel/fpu/xstate.c | 11 +++++++++++ > > > > > > 1 file changed, 11 insertions(+) > > > > > > > > > > > > diff --git a/arch/x86/kernel/fpu/xstate.c > > b/arch/x86/kernel/fpu/xstate.c > > > > > > index 76153dfb58c9..188323442b4d 100644 > > > > > > --- a/arch/x86/kernel/fpu/xstate.c > > > > > > +++ b/arch/x86/kernel/fpu/xstate.c > > > > > > @@ -855,6 +855,17 @@ void __init fpu__init_system_xstate(unsigned > > int > > > > > legacy_size) > > > > > > goto out_disable; > > > > > > } > > > > > > > > > > > > + if (boot_cpu_has(X86_FEATURE_USER_SHSTK) && > > > > > > + !(fpu_kernel_cfg.max_features & XFEATURE_MASK_CET_USER)) { > > > > > > + /* > > > > > > + * The kernel relies on XSAVES/XRSTORS to context switch > > shadow > > > > > > + * stack state. If this isn't present, disable user shadow > > > > > > + * stacks. > > > > > > + */ > > > > > > + pr_err("x86/fpu: CET_USER not supported in xstate when CET is > > > > > supported. Disabling shadow stacks.\n"); > > > > > > + setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK); > > > > > > > > > > Doesn't this apply to IBT as well? This code is also misplaced, as it needs > > to > > > > > live after at least this code: > > > > > > > > Good point, it likely does. I can't confirm that as I don't have IBT hardware, > > > > but assuming that a guest can see CET_IBT=1 this same problem would > > exist. > > > > > > Actually, I don't think this does apply to IBT as well. Per > > > Documentation/arch/x86/shstk.rst, only kernel IBT is currently supported by > > > Linux. And kernel IBT does not require either CET_USER or CET_KERNEL XSS > > > support from what I see. (CET_KERNEL is only for the shadow stack related > > > MSRs) > > > > KVM virtualizes IBT and SHSTK, for both user and kernel, and relies on the host > > kernel to save/restore IA32_U_CET. > > I think you're talking about a nested virt scenario is that right? FWIW, this isn't limited to running in a VM. Booting on bare metal with e.g. noxsaves=1 would lead to the same problematic scenario. > So KVM in L1 virtualizes IBT/SHSTK for L2 and relies on the L1 kernel to > save/restore IA32_UCET? And the concern is that if L1 doesn't support the > XSS components then this is broken. > > But it looks like kvm_setup_xss_caps() appears to check if host XSS includes Gah, -ENOCOFFEE, I forgot that KVM manually verifies that the kernel will context switch CET. > all the CET components and will clear X86_FEATURE_SHSTK/IBT if they aren't > present. So I think what you'd see is: > > L0: CPUID says SHSTK/IBT supported. XSS bits supported. > L1: CPUID says SHSTK/IBT supported. XSS bits not supported > L2: CPUID doesn't say SHSTK/IBT supported. > > Or did I misunderstand the scenario you're talking about?