Re: [PATCH v3 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Yao Zi <me@ziyao.cc>]

On Wed, Apr 08, 2026 at 04:28:01PM +0800, Chen Wang wrote:
> 
> On 4/5/2026 11:41 PM, Yao Zi wrote:
> > After talking to Inochi privately, I'll take the patch instead.
> > 
> > This series defines quirk flags for Cadence PCIe host driver to allow
> > disabling advertisement of ASPM L0s/L1 states by overriding LNKCAP
> > register, and set them in SG2042 PCIe driver since SG2042's
> > implementation is broken.
> > 
> > I've considered to re-write LNKCAP after cdns_pcie_host_setup() in
> > SG2042 platform glue, like what has been done in the v1 of patch.
> > However, cdns_pcie_host_setup() performs pci_host_probe(), which finally
> > invokes set_pcie_port_type() on the root port. It reads ASPM-related
> > LNKCAP, which might lead to dangling pci_dev.aspm_{l0s,l1}_support
> > values. Early PCI device fixup won't work for similar reasons, since the
> > fixup is performed in pci_setup_device() after calling
> > set_pcie_port_type().
> > 
> > It's hard to fix up the LNKCAP earlier than invokation of
> > cdns_pcie_host_setup() in SG2042's platform glue, either, since
> > the function also performs resource allocation/mapping, and we have no
> > access to the RC registers before it returns.
> > 
> > The safest solution which also depends on no PCI subsystem
> > implementation detail is to have the LNKCAP fixed up right before
> > informing the PCI subsystem of the device through pci_host_probe(), so
> > here come the quirk flags and the ASPM advertisement disabling logic
> > in the core Cadence PCIe driver.
> > 
> > This series is based on next-20260403, thanks for your time and review.
> > 
> > Changed from v2:
> > - Use flags to allow platform glues to inform the core driver that
> >    ASPM implementation is broken and should be disabled, instead of
> >    introducing platform-specific hooks to do so.
> > - Fix Co-developed-by tag in patch 2
> > - Link to v2: https://lore.kernel.org/linux-pci/20260227181925.52475-1-me@ziyao.cc/
> > 
> > Changed from v1:
> > - Disable L0s/L1 capabilities through LNKCAP instead of LNKCTL
> > - Introduce platform-specific init/deinit hooks (new PATCH 1) to
> >    realiably overwrite PCIe RC properties
> > - Link to v1: https://lore.kernel.org/all/20260109040756.731169-2-inochiama@gmail.com/
> > 
> > Changed from the original patch:
> > - Use driver to mask the ASPM advertisement
> > - Separate from the following patch
> >    https://lore.kernel.org/all/20251225100530.1301625-1-inochiama@gmail.com
> > 
> > Yao Zi (2):
> >    PCI: cadence: Add flags for disabling ASPM support advertisement
> >    PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports
> > 
> >   .../controller/cadence/pcie-cadence-host.c    |  7 +++++++
> >   drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++
> >   drivers/pci/controller/cadence/pcie-sg2042.c  |  2 ++
> >   3 files changed, 28 insertions(+)
> 
> BTW, I guess you might forget to post this patchset to
> sophgo@lists.linux.dev. Please remember this later.

Oops, yes. I blindly followed the output of get_maintainers.pl, which
doesn't mention Sophgo's mailing list when run against pcie-sg2042.c.

Maybe we should add pcie-sg2042.c to the "SOPHGO DEVICETREES and
DRIVERS" entry in MAINTAINERS file, or add a keyword for the entry?

> Thanks,
> 
> Chen
> 

Regards,
Yao Zi