[PATCH v3 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[PATCH v3 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Yao Zi]

After talking to Inochi privately, I'll take the patch instead.

This series defines quirk flags for Cadence PCIe host driver to allow
disabling advertisement of ASPM L0s/L1 states by overriding LNKCAP
register, and set them in SG2042 PCIe driver since SG2042's
implementation is broken.

I've considered to re-write LNKCAP after cdns_pcie_host_setup() in
SG2042 platform glue, like what has been done in the v1 of patch.
However, cdns_pcie_host_setup() performs pci_host_probe(), which finally
invokes set_pcie_port_type() on the root port. It reads ASPM-related
LNKCAP, which might lead to dangling pci_dev.aspm_{l0s,l1}_support
values. Early PCI device fixup won't work for similar reasons, since the
fixup is performed in pci_setup_device() after calling
set_pcie_port_type().

It's hard to fix up the LNKCAP earlier than invokation of
cdns_pcie_host_setup() in SG2042's platform glue, either, since
the function also performs resource allocation/mapping, and we have no
access to the RC registers before it returns.

The safest solution which also depends on no PCI subsystem
implementation detail is to have the LNKCAP fixed up right before
informing the PCI subsystem of the device through pci_host_probe(), so
here come the quirk flags and the ASPM advertisement disabling logic
in the core Cadence PCIe driver.

This series is based on next-20260403, thanks for your time and review.

Changed from v2:
- Use flags to allow platform glues to inform the core driver that
  ASPM implementation is broken and should be disabled, instead of
  introducing platform-specific hooks to do so.
- Fix Co-developed-by tag in patch 2
- Link to v2: https://lore.kernel.org/linux-pci/20260227181925.52475-1-me@ziyao.cc/

Changed from v1:
- Disable L0s/L1 capabilities through LNKCAP instead of LNKCTL
- Introduce platform-specific init/deinit hooks (new PATCH 1) to
  realiably overwrite PCIe RC properties
- Link to v1: https://lore.kernel.org/all/20260109040756.731169-2-inochiama@gmail.com/

Changed from the original patch:
- Use driver to mask the ASPM advertisement
- Separate from the following patch
  https://lore.kernel.org/all/20251225100530.1301625-1-inochiama@gmail.com

Yao Zi (2):
  PCI: cadence: Add flags for disabling ASPM support advertisement
  PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

 .../controller/cadence/pcie-cadence-host.c    |  7 +++++++
 drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++
 drivers/pci/controller/cadence/pcie-sg2042.c  |  2 ++
 3 files changed, 28 insertions(+)

-- 
2.53.0

[PATCH v3 1/2] PCI: cadence: Add flags for disabling ASPM support advertisement

[Yao Zi]

Add flags for disabling advertisement of ASPM L0s/L1 states by clearing
corresponding bits in Link Capabilities Register through the local
management bus, allowing ASPM to be disabled on platforms which don't
support it.

Signed-off-by: Yao Zi <me@ziyao.cc>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
---
 .../controller/cadence/pcie-cadence-host.c    |  7 +++++++
 drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index db3154c1eccb..0bc9e6e90e0e 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -147,6 +147,13 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
 	cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
 	cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
 
+	value = cdns_pcie_rp_readl(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP);
+	if (rc->quirk_broken_aspm_l0s)
+		value &= ~PCI_EXP_LNKCAP_ASPM_L0S;
+	if (rc->quirk_broken_aspm_l1)
+		value &= ~PCI_EXP_LNKCAP_ASPM_L1;
+	cdns_pcie_rp_writel(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP, value);
+
 	return 0;
 }
 
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 443033c607d7..32a5666204f5 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -115,6 +115,8 @@ struct cdns_pcie {
  * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
  * @ecam_supported: Whether the ECAM is supported
  * @no_inbound_map: Whether inbound mapping is supported
+ * @quirk_broken_aspm_l0s: Disable ASPM L0s support as quirk.
+ * @quirk_broken_aspm_l1: Disable ASPM L1 support as quirk.
  */
 struct cdns_pcie_rc {
 	struct cdns_pcie	pcie;
@@ -127,6 +129,8 @@ struct cdns_pcie_rc {
 	unsigned int		quirk_detect_quiet_flag:1;
 	unsigned int            ecam_supported:1;
 	unsigned int            no_inbound_map:1;
+	unsigned int            quirk_broken_aspm_l0s:1;
+	unsigned int            quirk_broken_aspm_l1:1;
 };
 
 /**
@@ -344,6 +348,21 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
 	return cdns_pcie_read_sz(addr, 0x2);
 }
 
+static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie,
+				       u32 reg, u32 value)
+{
+	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
+
+	cdns_pcie_write_sz(addr, 0x4, value);
+}
+
+static inline u32 cdns_pcie_rp_readl(struct cdns_pcie *pcie, u32 reg)
+{
+	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
+
+	return cdns_pcie_read_sz(addr, 0x4);
+}
+
 static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie,
 					   u32 reg, u8 value)
 {
-- 
2.53.0

Re: [PATCH v3 1/2] PCI: cadence: Add flags for disabling ASPM support advertisement

[Chen Wang]

On 4/5/2026 11:41 PM, Yao Zi wrote:
> Add flags for disabling advertisement of ASPM L0s/L1 states by clearing
> corresponding bits in Link Capabilities Register through the local
> management bus, allowing ASPM to be disabled on platforms which don't
> support it.
>
> Signed-off-by: Yao Zi <me@ziyao.cc>
> Tested-by: Han Gao <gaohan@iscas.ac.cn>
> ---
>   .../controller/cadence/pcie-cadence-host.c    |  7 +++++++
>   drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++
>   2 files changed, 26 insertions(+)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index db3154c1eccb..0bc9e6e90e0e 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -147,6 +147,13 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
>   	cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
>   	cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
>   
> +	value = cdns_pcie_rp_readl(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP);
> +	if (rc->quirk_broken_aspm_l0s)
> +		value &= ~PCI_EXP_LNKCAP_ASPM_L0S;
> +	if (rc->quirk_broken_aspm_l1)
> +		value &= ~PCI_EXP_LNKCAP_ASPM_L1;
> +	cdns_pcie_rp_writel(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP, value);
> +
>   	return 0;
>   }
>   
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 443033c607d7..32a5666204f5 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -115,6 +115,8 @@ struct cdns_pcie {
>    * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
>    * @ecam_supported: Whether the ECAM is supported
>    * @no_inbound_map: Whether inbound mapping is supported
> + * @quirk_broken_aspm_l0s: Disable ASPM L0s support as quirk.
> + * @quirk_broken_aspm_l1: Disable ASPM L1 support as quirk.
>    */
>   struct cdns_pcie_rc {
>   	struct cdns_pcie	pcie;
> @@ -127,6 +129,8 @@ struct cdns_pcie_rc {
>   	unsigned int		quirk_detect_quiet_flag:1;
>   	unsigned int            ecam_supported:1;
>   	unsigned int            no_inbound_map:1;
> +	unsigned int            quirk_broken_aspm_l0s:1;
> +	unsigned int            quirk_broken_aspm_l1:1;
>   };
>   
>   /**
> @@ -344,6 +348,21 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
>   	return cdns_pcie_read_sz(addr, 0x2);
>   }
>   
> +static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie,
> +				       u32 reg, u32 value)
> +{
> +	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
> +
> +	cdns_pcie_write_sz(addr, 0x4, value);
> +}
> +
> +static inline u32 cdns_pcie_rp_readl(struct cdns_pcie *pcie, u32 reg)
> +{
> +	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
> +
> +	return cdns_pcie_read_sz(addr, 0x4);
> +}
> +
>   static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie,
>   					   u32 reg, u8 value)
>   {

LGTM.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>

Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox.

Thanks,

Chen

[PATCH v3 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Yao Zi]

Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
states for devicetree platforms") force enable ASPM on all device tree
platform, the SG2042 root port breaks as it advertises L0s and L1
capabilities without supporting it.

Set ASPM quirks to disable advertisement of L0s and L1 support, so
it doesn't try to enable those states.

Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
Co-developed-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Yao Zi <me@ziyao.cc>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
---
 drivers/pci/controller/cadence/pcie-sg2042.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
index 0c50c74d03ee..4a2af4d0713e 100644
--- a/drivers/pci/controller/cadence/pcie-sg2042.c
+++ b/drivers/pci/controller/cadence/pcie-sg2042.c
@@ -48,6 +48,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev)
 	bridge->child_ops = &sg2042_pcie_child_ops;
 
 	rc = pci_host_bridge_priv(bridge);
+	rc->quirk_broken_aspm_l0s = 1;
+	rc->quirk_broken_aspm_l1 = 1;
 	pcie = &rc->pcie;
 	pcie->dev = dev;
 
-- 
2.53.0

Re: [PATCH v3 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Chen Wang]

On 4/5/2026 11:41 PM, Yao Zi wrote:
> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM
> states for devicetree platforms") force enable ASPM on all device tree
> platform, the SG2042 root port breaks as it advertises L0s and L1
> capabilities without supporting it.
>
> Set ASPM quirks to disable advertisement of L0s and L1 support, so
> it doesn't try to enable those states.
>
> Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
> Co-developed-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Yao Zi <me@ziyao.cc>
> Tested-by: Han Gao <gaohan@iscas.ac.cn>
> ---
>   drivers/pci/controller/cadence/pcie-sg2042.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
> index 0c50c74d03ee..4a2af4d0713e 100644
> --- a/drivers/pci/controller/cadence/pcie-sg2042.c
> +++ b/drivers/pci/controller/cadence/pcie-sg2042.c
> @@ -48,6 +48,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev)
>   	bridge->child_ops = &sg2042_pcie_child_ops;
>   
>   	rc = pci_host_bridge_priv(bridge);
> +	rc->quirk_broken_aspm_l0s = 1;
> +	rc->quirk_broken_aspm_l1 = 1;
>   	pcie = &rc->pcie;
>   	pcie->dev = dev;
>   

LGTM.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>

Tested-by: Chen Wang <unicorn_wang@outlook.com> on Pioneerbox.

Thanks,

Chen

Re: [PATCH v3 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Chen Wang]

On 4/5/2026 11:41 PM, Yao Zi wrote:
> After talking to Inochi privately, I'll take the patch instead.
>
> This series defines quirk flags for Cadence PCIe host driver to allow
> disabling advertisement of ASPM L0s/L1 states by overriding LNKCAP
> register, and set them in SG2042 PCIe driver since SG2042's
> implementation is broken.
>
> I've considered to re-write LNKCAP after cdns_pcie_host_setup() in
> SG2042 platform glue, like what has been done in the v1 of patch.
> However, cdns_pcie_host_setup() performs pci_host_probe(), which finally
> invokes set_pcie_port_type() on the root port. It reads ASPM-related
> LNKCAP, which might lead to dangling pci_dev.aspm_{l0s,l1}_support
> values. Early PCI device fixup won't work for similar reasons, since the
> fixup is performed in pci_setup_device() after calling
> set_pcie_port_type().
>
> It's hard to fix up the LNKCAP earlier than invokation of
> cdns_pcie_host_setup() in SG2042's platform glue, either, since
> the function also performs resource allocation/mapping, and we have no
> access to the RC registers before it returns.
>
> The safest solution which also depends on no PCI subsystem
> implementation detail is to have the LNKCAP fixed up right before
> informing the PCI subsystem of the device through pci_host_probe(), so
> here come the quirk flags and the ASPM advertisement disabling logic
> in the core Cadence PCIe driver.
>
> This series is based on next-20260403, thanks for your time and review.
>
> Changed from v2:
> - Use flags to allow platform glues to inform the core driver that
>    ASPM implementation is broken and should be disabled, instead of
>    introducing platform-specific hooks to do so.
> - Fix Co-developed-by tag in patch 2
> - Link to v2: https://lore.kernel.org/linux-pci/20260227181925.52475-1-me@ziyao.cc/
>
> Changed from v1:
> - Disable L0s/L1 capabilities through LNKCAP instead of LNKCTL
> - Introduce platform-specific init/deinit hooks (new PATCH 1) to
>    realiably overwrite PCIe RC properties
> - Link to v1: https://lore.kernel.org/all/20260109040756.731169-2-inochiama@gmail.com/
>
> Changed from the original patch:
> - Use driver to mask the ASPM advertisement
> - Separate from the following patch
>    https://lore.kernel.org/all/20251225100530.1301625-1-inochiama@gmail.com
>
> Yao Zi (2):
>    PCI: cadence: Add flags for disabling ASPM support advertisement
>    PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports
>
>   .../controller/cadence/pcie-cadence-host.c    |  7 +++++++
>   drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++
>   drivers/pci/controller/cadence/pcie-sg2042.c  |  2 ++
>   3 files changed, 28 insertions(+)

BTW, I guess you might forget to post this patchset to 
sophgo@lists.linux.dev. Please remember this later.

Thanks,

Chen

Re: [PATCH v3 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports

[Yao Zi]

On Wed, Apr 08, 2026 at 04:28:01PM +0800, Chen Wang wrote:
> 
> On 4/5/2026 11:41 PM, Yao Zi wrote:
> > After talking to Inochi privately, I'll take the patch instead.
> > 
> > This series defines quirk flags for Cadence PCIe host driver to allow
> > disabling advertisement of ASPM L0s/L1 states by overriding LNKCAP
> > register, and set them in SG2042 PCIe driver since SG2042's
> > implementation is broken.
> > 
> > I've considered to re-write LNKCAP after cdns_pcie_host_setup() in
> > SG2042 platform glue, like what has been done in the v1 of patch.
> > However, cdns_pcie_host_setup() performs pci_host_probe(), which finally
> > invokes set_pcie_port_type() on the root port. It reads ASPM-related
> > LNKCAP, which might lead to dangling pci_dev.aspm_{l0s,l1}_support
> > values. Early PCI device fixup won't work for similar reasons, since the
> > fixup is performed in pci_setup_device() after calling
> > set_pcie_port_type().
> > 
> > It's hard to fix up the LNKCAP earlier than invokation of
> > cdns_pcie_host_setup() in SG2042's platform glue, either, since
> > the function also performs resource allocation/mapping, and we have no
> > access to the RC registers before it returns.
> > 
> > The safest solution which also depends on no PCI subsystem
> > implementation detail is to have the LNKCAP fixed up right before
> > informing the PCI subsystem of the device through pci_host_probe(), so
> > here come the quirk flags and the ASPM advertisement disabling logic
> > in the core Cadence PCIe driver.
> > 
> > This series is based on next-20260403, thanks for your time and review.
> > 
> > Changed from v2:
> > - Use flags to allow platform glues to inform the core driver that
> >    ASPM implementation is broken and should be disabled, instead of
> >    introducing platform-specific hooks to do so.
> > - Fix Co-developed-by tag in patch 2
> > - Link to v2: https://lore.kernel.org/linux-pci/20260227181925.52475-1-me@ziyao.cc/
> > 
> > Changed from v1:
> > - Disable L0s/L1 capabilities through LNKCAP instead of LNKCTL
> > - Introduce platform-specific init/deinit hooks (new PATCH 1) to
> >    realiably overwrite PCIe RC properties
> > - Link to v1: https://lore.kernel.org/all/20260109040756.731169-2-inochiama@gmail.com/
> > 
> > Changed from the original patch:
> > - Use driver to mask the ASPM advertisement
> > - Separate from the following patch
> >    https://lore.kernel.org/all/20251225100530.1301625-1-inochiama@gmail.com
> > 
> > Yao Zi (2):
> >    PCI: cadence: Add flags for disabling ASPM support advertisement
> >    PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports
> > 
> >   .../controller/cadence/pcie-cadence-host.c    |  7 +++++++
> >   drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++
> >   drivers/pci/controller/cadence/pcie-sg2042.c  |  2 ++
> >   3 files changed, 28 insertions(+)
> 
> BTW, I guess you might forget to post this patchset to
> sophgo@lists.linux.dev. Please remember this later.

Oops, yes. I blindly followed the output of get_maintainers.pl, which
doesn't mention Sophgo's mailing list when run against pcie-sg2042.c.

Maybe we should add pcie-sg2042.c to the "SOPHGO DEVICETREES and
DRIVERS" entry in MAINTAINERS file, or add a keyword for the entry?

> Thanks,
> 
> Chen
> 

Regards,
Yao Zi