Re: PCIE

[Roland Dreier <rdreier@cisco.com>]

 > > i presume then i shouldn't be using IRQF_SHARED, if using MSI.
 > 
 > That's actually a really good question.
 > 
 > It is likely architecture dependant whether the PCI controller wires
 > unique MSI interrupts to shared cpu interrupt lines.

Yes, but current Linux drivers assume that MSI interrupts are
non-shared.  Certainly in my drivers I make that assumption, and from
a quick look neither tg3 nor e1000 sets IRQF_SHARED if they enable
MSI.

I think that if we run on a system where MSI interrupts may be shared,
then we should just have pci_enable_msi() fail.  If drivers have to
allow for shared MSI interrupts, then they lose most of the advantage
of MSI -- if I get an MSI but I don't know it came from my device, I
probably have to do an MMIO read to find out if it's mine or not and
also to preserve DMA ordering, which kills the main advantage of MSI.
And since MSIs are basically edge triggered, sharing vectors is going
to lead to all sorts of hassles.

 > I can imagine many systems where the cpu simply doesn't have enough
 > interrupt pins to uniquely identify every possible MSI interrupt
 > source.

I have a hard time imagining a PCI host bus controller that converts
MSI interrupts back to wire interrupts that go to pins on the CPU.
For one thing it would be hard to maintain the guarantee that
MSI interrupts can't pass DMAs.  And it would be an absolutely silly
architecture too.

 - R.