Re: 64 bit PCI access using MMX register -- how?

[Roland Dreier <rdreier@cisco.com>]

 > I think he was ok because he saved the MMX state by itself, except:
 > 
 > - There was no guarantee that the FPU is in MMX state, not x87 state
 > - He'll often get a lazy fpu save exception. This used to BUG() 
 > in some cases when invoked from kernel space (but that might have been
 > changed now). Better is to disable this explicitely around 
 > the access (like in kernel_fpu_begin()/end())
 > - Doing this all properly is fairly expensive and I suspect
 > just using a lock will be cheaper.

I had some code a long time ago that used SSE (I think movlps was the
opcode I chose) to get an atomic 64-bit PIO operation.  To do that, I
just needed to disable preemption and save/restore cr0 around the SSE
operation, and just save/restore the single xmm register I used.  Of
course it only works on CPUs that have SSE.  That avoids the nastiness
of x87/mmx state, but in the end a spinlock around two readl()s was
faster and a ton simpler, so I threw all that code away.

 - R.