From: Roland Dreier <rdreier@cisco.com>
To: "Moore\, Eric" <Eric.Moore@lsi.com>
Cc: <linux-kernel@vger.kernel.org>
Subject: Re: HELP: Is writeq an atomic operation??
Date: Fri, 02 May 2008 17:10:25 -0700 [thread overview]
Message-ID: <adak5ic2qoe.fsf@cisco.com> (raw)
In-Reply-To: <0631C836DBF79F42B5A60C8C8D4E822901047B4C@NAMAIL2.ad.lsil.com> (Eric Moore's message of "Fri, 2 May 2008 17:20:58 -0600")
> Under platforms where writeq is not defined, what should I do?
Umm... is it too late to change your chip design?
Seriously, for example on PowerPC 440SPe (which has a PCIe bus on a
32-bit PowerPC core), I don't know any way you can generate a 64-bit PCI
transaction. Even on 32-bit x86 I think you're stuck using something
ugly like MMX to do it.
Basically it's going to be architecture-dependent at best.
- R.
next prev parent reply other threads:[~2008-05-03 0:10 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-05-02 22:40 HELP: Is writeq an atomic operation?? Moore, Eric
2008-05-02 22:46 ` Roland Dreier
2008-05-03 0:42 ` H. Peter Anvin
2008-05-03 14:35 ` Alan Cox
2008-05-03 17:40 ` H. Peter Anvin
2008-05-03 22:37 ` Benjamin Herrenschmidt
2008-05-04 17:01 ` Roland Dreier
2008-05-02 22:50 ` Andi Kleen
2008-05-02 23:03 ` Moore, Eric
2008-05-02 23:13 ` Andi Kleen
2008-05-02 23:04 ` Roland Dreier
2008-05-02 23:20 ` Moore, Eric
2008-05-03 0:10 ` Roland Dreier [this message]
2008-05-02 23:12 ` Jesse Barnes
2008-05-03 0:41 ` H. Peter Anvin
[not found] <0631C836DBF79F42B5A60C8C8D4E822901047B1D@NAMAIL2.ad.lsil.com>
2008-05-02 22:32 ` David Miller
2008-05-02 22:43 ` Roland Dreier
2008-05-02 22:49 ` David Miller
2008-05-02 22:49 ` Moore, Eric
2008-05-02 22:53 ` Roland Dreier
2008-05-02 23:13 ` Moore, Eric
2008-05-02 23:21 ` Roland Dreier
2008-05-02 23:31 ` Moore, Eric
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