Re: [PATCH] mm/arm: pgtable: remove young bit check for pte_valid_user

Russell King (Oracle)
2026-04-09T14:15:58Z

On Thu, Apr 09, 2026 at 03:54:45PM +0300, Brian Ruley wrote:
> Fixes cache desync, which can cause undefined instruction,
> translation and permission faults under heavy memory use.
>
> This is an old bug introduced in commit 1971188aa196 ("ARM: 7985/1: mm:
> implement pte_accessible for faulting mappings"), which included a check
> for the young bit of a PTE. The underlying assumption was that old pages
> are not cached, therefore, `__sync_icache_dcache' could be skipped
> entirely.
>
> However, under extreme memory pressure, page migrations happen
> frequently and the assumption of uncached "old" pages does not hold.

The first thing to point out is that PTEs that are marked as "old" are
not mapped into userspace. They need to take a fault to be marked
young, which will involve another call to set_pte(), at which point
pte_valid_user() should return true. Your assumption that this is
about "old" pages being uncached is totally incorrect - there has
never been such an assumption.

> Especially for systems that do not have swap, the migrated pages are
> unequivocally marked old. This presents a problem, as it is possible
> for the original page to be immediately mapped to another VA that
> happens to share the same cache index in VIPT I-cache (we found this
> bug on Cortex-A9). Without cache invalidation, the CPU will see the
> old mapping whose physical page can now be used for a different
> purpose, as illustrated below:

>
> Core Physical Memory
> +-------------------------------+ +------------------+
> | TLB | | |
> | VA_A 0xb6e6f -> pfn_q | | pfn_q: code |
> +-------------------------------+ +------------------+
> | I-cache |
> | set[VA_A bits] | tag=pfn_q |
> +-------------------------------+
>
> migrate (kcompactd):
> 1. copy pfn_q --> pfn_r
> 2. free pfn_q
> 3. pte: VA_a -> pfn_r
> 4. pte_mkold(pte) --> !young
> 5. ICIALLUIS skipped (because !young)

At this point, the hardware PTE will be set to zero and the TLB
invalidated. This _should_ mean that any future access should result
in a page permission fault being raised. That will then provoke the
MM to mark the PTE young, which will then result in set_ptes()
being called, and thus __sync_icache_dcache() will be called for
the _neew_ pte (which will be for pfn_r.)

>
> pfn_src reused (OOM pressure):
> pte: VA_B -> pfn_q (different code)
>
> bug:
> Core Physical Memory
> +-------------------------------+ +------------------+
> | TLB (empty) | | pfn_r: old code |
> +-------------------------------+ | pfn_q: new code |
> | I-cache | +------------------+
> | set[VA_A bits] | tag=pfn_q |<--- wrong instructions
> +-------------------------------+
>
> This was verified on ba16-based board (i.MX6Quad/Dual, Cortex-A9) by
> instrumenting the migration code to track recently migrated pages in a
> ring buffer and then dumping them in the undefined instruction fault
> handler. The bug can be triggered with `stress-ng':
>
> stress-ng --vm 4 --vm-bytes 2G --vm-method zero-one --verify
>
> Note that the system we tested on has only 2G of memory, so the test
> triggered the OOM-killer in our case.

So you're saying that stress-ng doesn't reproduce this bug but triggers
the OOM-killer... confused.

Cortex-A9 has been around for a long time - I have systems that still
use Cortex-A9 every day without swap, and they have been rock solid.

If there was a bug like this, I would've expected to see problems, but
I'm not... so, I'm not convinced there's a problem here.