From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3F88131327A for ; Thu, 9 Apr 2026 16:27:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775752057; cv=none; b=ggIbhUHBouM/PxcnodopQG3OB62NYpR4ay1IyKd8utiKBO59aCT3Aex+I2nO+FIzkJZDP9e1zNvadaKfX/YEqp7S/uFcg3XgqafdB3lkTYmEoaoQG9N9herks9v4E6w8uVw+S3VMN6F76LRnB1zouE9FeQfdTmXPZsTJkhTSwqQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775752057; c=relaxed/simple; bh=PcwHOgTB9v53Jq+fpgtd844vKQY3L9N5xVo3GA34vtA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Ut2jaB9aqeujhIGbV+4nb2D0kusyn7MKtI9e1bOXqsiCDtt5exXHPOKPdS7NkHtld4K+BAMfpSUDhMEMj3jktSWaBFf0bEWnvY5v28WGD8AhgAXIKBakBtNGRTDoQjdlvvLo/y77EAZVrEzgmC56qIZGX2kBcCSLINlJ+5yX1JE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=GhMdL4zs; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="GhMdL4zs" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D0A96452F; Thu, 9 Apr 2026 09:27:28 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 42F9B3F641; Thu, 9 Apr 2026 09:27:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775752054; bh=PcwHOgTB9v53Jq+fpgtd844vKQY3L9N5xVo3GA34vtA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=GhMdL4zsviRSrkAvCluaZ4CN2guSJEMEzeGl6ns2I7u4o1Q62MLRtOtH+Yp+cWRgc Ov36T71k3Ojdcg664ExrE1EzqdCvlZ/8SrzMYQMqiKzTE3fQgTcfbaJZEjLM0ovUEA kpp/r1COurflGLA/F17bNg6OHddGlMD7jDmQ2F7U= Date: Thu, 9 Apr 2026 17:27:30 +0100 From: Catalin Marinas To: "David Hildenbrand (Arm)" Cc: Muhammad Usama Anjum , Will Deacon , "Matthew Wilcox (Oracle)" , Thomas Huth , Andrew Morton , Lance Yang , Yeoreum Yun , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: mte: Skip TFSR_EL1 checks and barriers in synchronous tag check mode Message-ID: References: <20260311175054.3889093-1-usama.anjum@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Mar 25, 2026 at 12:46:40PM +0100, David Hildenbrand wrote: > On 3/11/26 18:50, Muhammad Usama Anjum wrote: > > In MTE synchronous mode, tag check faults are reported as immediate > > Data Abort exceptions. The TFSR_EL1.TF1 bit is never set, since faults > > never go through the asynchronous path. Therefore, reading TFSR_EL1 > > and executing data and instruction barriers on kernel entry, exit, > > context switch, and suspend is unnecessary overhead in sync mode. > > > > The exit path (mte_check_tfsr_exit) and the assembly paths > > (check_mte_async_tcf / clear_mte_async_tcf in entry.S) already had this > > check. > > Right, that's for user space (TFSR_EL1.TF0 IIUC). What you are adding is > for KASAN. Maybe make that clearer. Yeah, I'll tweak the commit message a bit. Even system_uses_mte_async_or_asymm_mode() should be renamed to something resembling kasan but I'll leave the function name as is for now. -- Catalin