From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4A56334C08; Fri, 10 Apr 2026 06:27:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775802472; cv=none; b=ZiHUjMBbmBIDJygzuo7xLwdHLBlBJ8qU4VQROzKp61JnYQjipsthlIz0TJFadnrIbhQ9lbTlaHtPmX3pEbI6aQnu9YWTb/GPMviY69znSbLQazXb8UHheR3zG8d5ik2Ku4DUIWNaBhqokQP384mTDXS1Dp23INvtTCaesg2l8Ys= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775802472; c=relaxed/simple; bh=ajthKdkAGwRhclYQfXtnXrA/phsT3uVTk3g+JGYsSm8=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=dNko+byoT+3ayZWYNSxdD62BTainL/RZm32q5Ju0vjZINDHgW6wtgJ+lS0mcagUFmTTJuoIWcWgVXO4eGJRm6/sNJadshOBJxIJJtoCCQPPNt6kJC63mwtzLG42fh1TiCYR6QkeffIpH08vOKcH+xLFeLwDuPNHt+/perHKhz9M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XhzjfMDT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XhzjfMDT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32E00C19421; Fri, 10 Apr 2026 06:27:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775802472; bh=ajthKdkAGwRhclYQfXtnXrA/phsT3uVTk3g+JGYsSm8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=XhzjfMDTjlPhnTwAKDqk9FKNM1gM6b5BBfQ7DCXXiCtElWfbwPWTeYgG50Kgkac9i TBDa7zpHv7cp7DbNDee2V3htlF8K8ihWxvTGCvFrAywF/6pCpEOALM21tzIAYsPxmK cR3rkbIkCojZw0UpM8O4+S8BGlhX9Dxl5CZu9S1fOC+cHsMEmp/Wkr42xaSTA4nJAp Yob2/HbJdnlSPyoDE46iVJ1GJkQtxOwxbIB5YxXPUodUEsMutaCCO8iG2WE9vnaZ9v z2pJJbnPpkdpbkJIH15E8VsNfRTsN5qm2oXr2PrJ3M0qdy6sWvGIDZ1KeRzcNy2YUp rhI1X8J3mRrug== Date: Fri, 10 Apr 2026 08:27:49 +0200 From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= To: Andrea della Porta Cc: linux-pwm@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Naushir Patuck , Stanimir Varbanov Subject: Re: [PATCH 2/3] pwm: rp1: Add RP1 PWM controller driver Message-ID: References: <28e29fbfc20c0b8a115d006233c2759d8f49e639.1775223441.git.andrea.porta@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="d3hvim2dtzodhjoa" Content-Disposition: inline In-Reply-To: --d3hvim2dtzodhjoa Content-Type: text/plain; protected-headers=v1; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH 2/3] pwm: rp1: Add RP1 PWM controller driver MIME-Version: 1.0 Hello Andrea, On Thu, Apr 09, 2026 at 06:16:41PM +0200, Andrea della Porta wrote: > On 23:45 Sun 05 Apr , Uwe Kleine-K=F6nig wrote: > > On Fri, Apr 03, 2026 at 04:31:55PM +0200, Andrea della Porta wrote: > > > +static void rp1_pwm_free(struct pwm_chip *chip, struct pwm_device *p= wm) > > > +{ > > > + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); > > > + u32 value; > > > + > > > + value =3D readl(rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm)); > > > + value &=3D ~PWM_MODE_MASK; > > > + writel(value, rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm)); > > > + > > > + rp1_pwm_apply_config(chip, pwm); > >=20 > > What is the purpose of this call? >=20 > To update the configuration on the next PWM strobe in order to avoid > glitches. I'll add a short comment in the code. =2Epwm_free() should not touch the hardware configuration. Changing the pinmuxing (which I guess is the purpose of clearing PWM_MODE_MASK) is somewhat a grey area. If that saves energy, that's okish. Otherwise not interfering with the operation of the PWM (e.g. to keep a display on during kexec or so) is preferred. > > > +static int rp1_pwm_resume(struct device *dev) > > > +{ > > > + struct rp1_pwm *rp1 =3D dev_get_drvdata(dev); > > > + > > > + return clk_prepare_enable(rp1->clk); > >=20 > > Hmm, if this fails and then the driver is unbound, the clk operations > > are not balanced. >=20 > I'll add some flags to check if the clock is really enabled or not. To be honest, I guess that is a problem of several drivers, not only in drivers/pwm. If this complicates the driver, I guess addressing this isn't very critical. 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