Re: [PATCH 1/2] dt-bindings: pwm: clk-pwm: add optional GPIO and pinctrl properties

Conor Dooley
2026-04-09T15:51:22Z

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On Mon, Apr 06, 2026 at 11:50:01PM +0800, Xilin Wu wrote:
> The clk-pwm driver cannot produce constant output levels (0% or 100%
> duty cycle, or disabled state) through the clock hardware alone - the
> actual pin level when the clock is off is undefined and
> hardware-dependent.
>
> Document optional gpios, pinctrl-names, pinctrl-0, and pinctrl-1
> properties that allow the driver to switch the pin between clock
> function mux (for normal PWM output) and GPIO mode (to drive a
> deterministic constant level).
>
> Signed-off-by: Xilin Wu <sophon@radxa.com>

This seems reasonable enough to me, but the PWM maintainers should
defintely make sure this fits the ideology of the device.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

> ---
> Documentation/devicetree/bindings/pwm/clk-pwm.yaml | 36 +++++++++++++++++++++-
> 1 file changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
> index ec1768291503..2a0e3e02d27b 100644
> --- a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
> +++ b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml
> @@ -15,6 +15,11 @@ description: |
> It's often possible to control duty-cycle of such clocks which makes them
> suitable for generating PWM signal.
>
> + Optionally, a GPIO and pinctrl states can be provided. When a constant
> + output level is needed (0%, 100%, or disabled), the pin is switched to
> + GPIO mode to drive the level directly. For normal PWM output the pin is
> + switched back to its clock function mux.
> +
> allOf:
> - $ref: pwm.yaml#
>
> @@ -29,6 +34,26 @@ properties:
> "#pwm-cells":
> const: 2
>
> + gpios:
> + description:
> + Optional GPIO used to drive a constant level when the PWM output is
> + disabled or set to 0% / 100% duty cycle. When provided, pinctrl states
> + "default" (clock mux) and "gpio" must also be defined.
> + maxItems: 1
> +
> + pinctrl-names: true
> +
> + pinctrl-0:
> + description: Pin configuration for clock function mux (normal PWM).
> + maxItems: 1
> +
> + pinctrl-1:
> + description: Pin configuration for GPIO mode (constant level output).
> + maxItems: 1
> +
> +dependencies:
> + gpios: [ pinctrl-0, pinctrl-1 ]
> +
> unevaluatedProperties: false
>
> required:
> @@ -41,6 +66,15 @@ examples:
> compatible = "clk-pwm";
> #pwm-cells = <2>;
> clocks = <&gcc 0>;
> - pinctrl-names = "default";
> + };
> +
> + - |
> + pwm {
> + compatible = "clk-pwm";
> + #pwm-cells = <2>;
> + clocks = <&gcc 0>;
> + pinctrl-names = "default", "gpio";
> pinctrl-0 = <&pwm_clk_flash_default>;
> + pinctrl-1 = <&pwm_clk_flash_gpio>;
> + gpios = <&tlmm 32 0>;
> };
>
> --
> 2.53.0
>

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