Re: [PATCH v2 1/4] perf/x86/intel: Don't write PEBS_ENABLED on host<=>guest xfers if CPU has isolation

[Sean Christopherson <seanjc@google.com>]

On Mon, Apr 27, 2026, Dapeng Mi wrote:
> On 4/24/2026 1:59 AM, Jim Mattson wrote:
> >>  arch/x86/events/intel/core.c | 42 ++++++++++++++++++++----------------
> >>  1 file changed, 23 insertions(+), 19 deletions(-)
> >>
> >> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> >> index 793335c3ce78..002d809f82ef 100644
> >> --- a/arch/x86/events/intel/core.c
> >> +++ b/arch/x86/events/intel/core.c
> >> @@ -4999,12 +4999,15 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
> >>         struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
> >>         u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
> >>         u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
> >> -       int global_ctrl, pebs_enable;
> >> +       u64 guest_pebs_mask = pebs_mask & ~cpuc->intel_ctrl_host_mask;
> >> +       int global_ctrl;
> > Is it worth noting somewhere that pebs_ept is not supported on any
> > CPUs with PMU version < 5, where a single event can set two
> > PEBS_ENABLE bits (cf. intel_pmu_pebs_enable)?

Is that a hardware limitation, or a "perf hasn't added pebs_ept for PMU v5 yet"
thing?  I assume it's the latter?

> >> +       /*
> >> +        * Disable counters where the guest PMC is different than the host PMC
> >> +        * being used on behalf of the guest, as the PEBS record includes
> >> +        * PERF_GLOBAL_STATUS, i.e. the guest will see overflow status for the
> >> +        * wrong counter(s).  Similarly, disallow PEBS in the guest if the host
> >> +        * is using PEBS, to avoid bleeding host state into PEBS records.
> >> +        */
> >> +       guest_pebs_mask &= kvm_pmu->pebs_enable & ~kvm_pmu->host_cross_mapped_mask;
> >> +       if (pebs_mask & ~cpuc->intel_ctrl_guest_mask)
> >> +               guest_pebs_mask = 0;
> > I don't understand this clause. IIUC, it says that if we don't have
> > any exclude-host PEBS events, then clear PEBS_ENABLE for the guest.
> 
> I suppose it says all guest PEBS events need to be disabled if there is any
> event using PEBS on host side, and it's clearing GLOBAL_CTRL instead of
> PEBS_ENABLE to disable guest PEBS events. 

Yeah, but why disable _everything_?

> > Yes, any guest-programmed PEBS event should be exclude-host, but if
> > there is an inconsistency, shouldn't we apply a mask? What if there is
> > only one exclude-host PEBS event, but there are two bits set in
> > guest_pebs_mask?

I'm confused about this as well.  The comment above about not bleeding host state
into the PEBS records is my best guess (and it's probably not a very good guess)
as to why the code does what it does.  The changelog from commit 854250329c02
("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations") just says:
    
    The guest PEBS will be disabled when some users try to perf KVM and
    its user-space through the same PEBS facility 

That doesn't entirely make sense to me though, because I would think disabling
the host counters iva GLOBAL_CTRL would suffice.  I.e. there's no need to disallow
PEBS in the guest just because the host is also using PEBS.  But I can't think of
any other reason to fully disable PEBS.

FWIW, I was going off the previous code which effectively did:

	if (cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask) {
		/* Disable guest PEBS if host PEBS is enabled. */
		arr[pebs_enable].guest = 0;
	}

One idea would be to add a FIXME, and then address the FIXME in a follow-up patch
(in the same series)?  And then see what breaks? :-)