From: Krzysztof Kozlowski <krzk@kernel.org>
To: Laura Nao <laura.nao@collabora.com>,
mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de,
richardcochran@gmail.com
Cc: guangjie.song@mediatek.com, wenst@chromium.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
kernel@collabora.com
Subject: Re: [PATCH v2 10/29] dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding
Date: Tue, 24 Jun 2025 18:03:01 +0200 [thread overview]
Message-ID: <ae13aeea-bf44-49e5-82c6-5e369ea96d84@kernel.org> (raw)
In-Reply-To: <20250624143220.244549-11-laura.nao@collabora.com>
On 24/06/2025 16:32, Laura Nao wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> Add a binding for the PEXTP0/1 and UFS reset controllers found in
> the MediaTek MT8196 Chromebook SoC.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Laura Nao <laura.nao@collabora.com>
> ---
> .../reset/mediatek,mt8196-resets.h | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
> create mode 100644 include/dt-bindings/reset/mediatek,mt8196-resets.h
No improvements.
<form letter>
This is a friendly reminder during the review process.
It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.
Thank you.
</form letter>
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-06-24 16:03 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 14:31 [PATCH v2 00/29] Add support for MT8196 clock controllers Laura Nao
2025-06-24 14:31 ` [PATCH v2 01/29] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-06-24 14:31 ` [PATCH v2 02/29] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-06-24 14:31 ` [PATCH v2 03/29] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-06-24 14:31 ` [PATCH v2 04/29] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-06-24 14:31 ` [PATCH v2 05/29] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-06-24 14:31 ` [PATCH v2 06/29] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-06-24 14:31 ` [PATCH v2 07/29] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-06-24 14:31 ` [PATCH v2 08/29] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-06-24 14:32 ` [PATCH v2 09/29] dt-bindings: clock: mediatek: Describe MT8196 peripheral clock controllers Laura Nao
2025-06-24 16:02 ` Krzysztof Kozlowski
2025-06-25 8:20 ` AngeloGioacchino Del Regno
2025-06-25 8:57 ` Krzysztof Kozlowski
2025-06-25 9:45 ` AngeloGioacchino Del Regno
2025-06-25 11:05 ` Krzysztof Kozlowski
2025-06-25 12:42 ` AngeloGioacchino Del Regno
2025-06-27 8:37 ` Krzysztof Kozlowski
2025-06-30 9:21 ` AngeloGioacchino Del Regno
2025-06-25 11:06 ` Krzysztof Kozlowski
2025-06-25 12:48 ` AngeloGioacchino Del Regno
2025-06-27 8:44 ` Krzysztof Kozlowski
2025-06-24 14:32 ` [PATCH v2 10/29] dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding Laura Nao
2025-06-24 16:03 ` Krzysztof Kozlowski [this message]
2025-06-24 16:04 ` Krzysztof Kozlowski
2025-06-25 8:48 ` Laura Nao
2025-06-24 14:32 ` [PATCH v2 11/29] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-06-24 14:32 ` [PATCH v2 12/29] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-07-15 4:53 ` Chen-Yu Tsai
2025-07-15 5:26 ` Chen-Yu Tsai
2025-06-24 14:32 ` [PATCH v2 13/29] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-06-24 14:32 ` [PATCH v2 14/29] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-07-15 7:28 ` Chen-Yu Tsai
2025-07-18 8:31 ` Chen-Yu Tsai
2025-07-22 10:52 ` Laura Nao
2025-06-24 14:32 ` [PATCH v2 15/29] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-06-24 14:32 ` [PATCH v2 16/29] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-06-24 14:32 ` [PATCH v2 17/29] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-06-24 14:32 ` [PATCH v2 18/29] clk: mediatek: Add MT8196 adsp " Laura Nao
2025-07-15 4:36 ` Chen-Yu Tsai
2025-06-24 14:32 ` [PATCH v2 19/29] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-06-24 14:32 ` [PATCH v2 20/29] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-06-24 14:32 ` [PATCH v2 21/29] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-06-24 14:32 ` [PATCH v2 22/29] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-06-29 20:56 ` kernel test robot
2025-06-24 14:32 ` [PATCH v2 23/29] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-06-24 14:32 ` [PATCH v2 24/29] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-06-24 14:32 ` [PATCH v2 25/29] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-06-24 14:32 ` [PATCH v2 26/29] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-06-24 14:32 ` [PATCH v2 27/29] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-06-24 14:32 ` [PATCH v2 28/29] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-06-24 14:32 ` [PATCH v2 29/29] clk: mediatek: Add MT8196 vencsys " Laura Nao
2025-06-24 15:49 ` [PATCH v2 00/29] Add support for MT8196 clock controllers Nícolas F. R. A. Prado
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