From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Mike Leach <mike.leach@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
James Clark <james.clark@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
Jinlong Mao <jinlong.mao@oss.qualcomm.com>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, Jie Gan <quic_jiegan@quicinc.com>
Subject: Re: [PATCH v4 03/10] coresight: tmc: add etr_buf_list to store allocated etr_buf
Date: Wed, 6 Aug 2025 08:32:35 +0800 [thread overview]
Message-ID: <ae3a482b-2b8c-4390-a950-f9612303003d@oss.qualcomm.com> (raw)
In-Reply-To: <CAJ9a7VijwFKiaZzKsSKPynWapA3ik9d7JLeE+yVNFB0T62iH-Q@mail.gmail.com>
On 8/5/2025 6:15 PM, Mike Leach wrote:
> Hi
>
> On Fri, 25 Jul 2025 at 11:08, Jie Gan <jie.gan@oss.qualcomm.com> wrote:
>>
>> Add a list to store allocated etr_buf.
>>
>> The byte-cntr functionality requires two etr_buf to receive trace data.
>> The active etr_buf collects the trace data from source device, while the
>> byte-cntr reading function accesses the deactivated etr_buf after is
>> has been filled and synced, transferring data to the userspace.
>>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>> .../hwtracing/coresight/coresight-tmc-core.c | 1 +
>> drivers/hwtracing/coresight/coresight-tmc.h | 19 +++++++++++++++++++
>> 2 files changed, 20 insertions(+)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
>> index be964656be93..4d249af93097 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
>> @@ -830,6 +830,7 @@ static int __tmc_probe(struct device *dev, struct resource *res)
>> idr_init(&drvdata->idr);
>> mutex_init(&drvdata->idr_mutex);
>> dev_list = &etr_devs;
>> + INIT_LIST_HEAD(&drvdata->etr_buf_list);
>> break;
>> case TMC_CONFIG_TYPE_ETF:
>> desc.groups = coresight_etf_groups;
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
>> index 6541a27a018e..52ee5f8efe8c 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc.h
>> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
>> @@ -208,6 +208,21 @@ struct tmc_resrv_buf {
>> s64 len;
>> };
>>
>> +/**
>> + * @sysfs_buf: Allocated sysfs_buf.
>> + * @is_free: Indicates whether the buffer is free to choose.
>> + * @reading: Indicates whether the buffer is reading.
>> + * @pos: Position of the buffer.
>> + * @node: Node in etr_buf_list.
>> + */
>> +struct etr_buf_node {
>> + struct etr_buf *sysfs_buf;
>> + bool is_free;
>> + bool reading;
>> + loff_t pos;
>> + struct list_head node;
>> +};
>> +
>> /**
>> * struct tmc_drvdata - specifics associated to an TMC component
>> * @pclk: APB clock if present, otherwise NULL
>> @@ -242,6 +257,8 @@ struct tmc_resrv_buf {
>> * (after crash) by default.
>> * @crash_mdata: Reserved memory for storing tmc crash metadata.
>> * Used by ETR/ETF.
>> + * @etr_buf_list: List that is used to manage allocated etr_buf.
>> + * @reading_node: Available buffer for byte-cntr reading.
>> */
>> struct tmc_drvdata {
>> struct clk *pclk;
>> @@ -271,6 +288,8 @@ struct tmc_drvdata {
>> struct etr_buf *perf_buf;
>> struct tmc_resrv_buf resrv_buf;
>> struct tmc_resrv_buf crash_mdata;
>> + struct list_head etr_buf_list;
>> + struct etr_buf_node *reading_node;
>
> Potential simplification:-
> do you need both reading_node here and reading in the etr_buf_node?
> reading_node handles the logic for which buffer is being read, while
> is_free handles the empty/full logic - reading seems unneeded?
Yes, you are right. I checked the usage of reading. It can be replaced
by reading_node in switch function.
I will simplify this patch in next version.
Thanks,
Jie
>
>> };
>>
>> struct etr_buf_operations {
>> --
>> 2.34.1
>>
>
> regards
>
> Mike
>
next prev parent reply other threads:[~2025-08-06 0:32 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-25 10:07 [PATCH v4 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-07-25 10:07 ` [PATCH v4 01/10] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-08-05 9:55 ` Mike Leach
2025-07-25 10:07 ` [PATCH v4 02/10] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-08-05 9:57 ` Mike Leach
2025-07-25 10:07 ` [PATCH v4 03/10] coresight: tmc: add etr_buf_list to store allocated etr_buf Jie Gan
2025-08-05 10:15 ` Mike Leach
2025-08-06 0:32 ` Jie Gan [this message]
2025-07-25 10:08 ` [PATCH v4 04/10] coresight: tmc: add create/delete functions for etr_buf_node Jie Gan
2025-08-05 10:27 ` Mike Leach
2025-08-06 0:45 ` Jie Gan
2025-07-25 10:08 ` [PATCH v4 05/10] coresight: tmc: Introduce tmc_read_ops to wrap read operations Jie Gan
2025-08-05 10:55 ` Mike Leach
2025-08-06 6:30 ` Jie Gan
2025-08-06 6:56 ` Mike Leach
2025-07-25 10:08 ` [PATCH v4 06/10] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-07-25 10:08 ` [PATCH v4 07/10] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-07-25 10:08 ` [PATCH v4 08/10] coresight: add a new function in helper_ops Jie Gan
2025-08-05 12:28 ` Mike Leach
2025-08-05 12:30 ` Mike Leach
2025-08-06 0:35 ` Jie Gan
2025-08-06 8:32 ` Jie Gan
2025-07-25 10:08 ` [PATCH v4 09/10] coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops Jie Gan
2025-07-25 10:08 ` [PATCH v4 10/10] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Jie Gan
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