From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from hall.aurel32.net (hall.aurel32.net [195.154.119.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35DE919CD0A for ; Sun, 26 Apr 2026 12:21:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.154.119.183 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777206075; cv=none; b=IqyOIeidEqzgz2sJ9GtjVftIHdEVTdYlP7JZqOUQpweyky6t4bnYYFHGziT9MkPScx8bep0467LFeJqvtFbBylgPImFKZvr3Ok1Sd2YgWG4Q6wWqDnK+wEbZQekMF/b9OAhLyItsltSlzwLSy+bjSMXqOmUUxHOzVyPX4rfbH/M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777206075; c=relaxed/simple; bh=UPxofDRPtU89ltCTNH7tbSwUJY6GdD/nNcIx9FJpgJQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=QuItITekdAVThI7AU5Yb76Khlb+EHpk25kMIn3X4Yx07RS0I2LK8lZSV4kH9Rd0IlH2WYRjFPQPWY0+oLGRMoVFK5DurM8BT8eU3oHpEgaPyUzQPQin9o7dT1+9r2wsMBSGBJX0BPUeL7Ga+IOKex4/uOGGxn01RXlez0R7EAIk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=aurel32.net; spf=pass smtp.mailfrom=aurel32.net; dkim=pass (2048-bit key) header.d=aurel32.net header.i=@aurel32.net header.b=HC7lSSSy; arc=none smtp.client-ip=195.154.119.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=aurel32.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aurel32.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aurel32.net header.i=@aurel32.net header.b="HC7lSSSy" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=In-Reply-To:Content-Type:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Content-Transfer-Encoding:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=045nMfVZbPU9T3swkBuoxApzDz8BfdAaxEnKeY7QH1s=; b=HC7lSSSyrXVLQKdOdYHjXZYBiN ZjLmvHgjFYqLfbxwIUBWECzBvSd5pjQ/z5nmMjmRIcTfzKQzw2KUOqHkkteL0nWizfQKEkvac+ldc vSHpjIeyqb8MQF+6q+jMGvhwyaiqasuLVC2o1ILg8iBQ9xHU1S+n5MLejbxxCVFJOyxe8DQ/XsM14 NY2Z2Vft0pMgWOlWFaRLaXi6MhltizF5KPhWp6trH8BQKeIw8UjtuYmNPyyGKTXU4W/g/Js4VcDlt DN0EJWqIv1xBPUX+HVEVJjUlC+EumRRXpBgoeXMeSwdkaU36jo4WMfU0ADRuCKGjGDjvst2mD577S NrtZQGMw==; Received: from authenticated user by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wGyTm-00000003vnN-3Le1; Sun, 26 Apr 2026 14:20:54 +0200 Date: Sun, 26 Apr 2026 14:20:54 +0200 From: Aurelien Jarno To: Anand Moon Cc: Samuel Holland , Troy Mitchell , Vivian Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC] riscv: disable local interrupts and stop other CPUs before restart Message-ID: Mail-Followup-To: Anand Moon , Samuel Holland , Troy Mitchell , Vivian Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260311-v7-0-rc1-rv-dis-int-before-restart-v1-1-bc46b4351cac@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.13 (2024-03-09) Hi Anand, On 2026-04-25 23:12, Anand Moon wrote: > Hi All, > > On Fri, 24 Apr 2026 at 02:21, Aurelien Jarno wrote: > > > > Hi, > > > > On 2026-03-16 08:19, Samuel Holland wrote: > > > Hi Troy, > > > > > > On 2026-03-16 2:23 AM, Troy Mitchell wrote: > > > >> I think the reason we ended up with the "unsafe" implementations of the > > > >> reboot/shutdown functions is that on the backend it is usually SBI SRST > > > >> calls, which can protect itself from other CPUs and interrupts. Since on > > > >> K1 we're going to be poking I2C directly, we run into the problem > > > >> described above. So all of these should disable interrupts and stop > > > >> other CPUs before calling the handlers, and can't assume the handlers > > > >> are all SBI SRST. > > > > Yes, we cannot assume that all platforms rely on this. > > > > > > Why isn't K1 using the SBI SRST extension? Resetting the platform from S-mode > > > directly causes problems if you ever want to run another supervisor domain (for > > > example a TEE or EFI runtime services), which may need to clean up before a > > > system reset. > > > > > > As you mention, other platforms use the standard SBI SRST interface, event if > > > they need to poke a PMIC to perform a system reset. Is there something > > > preventing K1 from following this path? > > > > I went this path and submitted a patchset to OpenSBI mailing list doing > > that: > > https://lore.kernel.org/opensbi/20260419150857.2705843-1-aurelien@aurel32.net/T/#t > > > I just wanted to check if we can use the latest OpenSBI image with > vendor u-boot ? > If so, can you share the details of flash the u-boot and OpenSBI binaries? . That is a good question, and no this doesn't work out of the box. > I was working on the watchdog driver, and the system hangs at reboot > So, what changes do we need to make in OpenSBI to handle this issue? This can be addressed either by making OpenSBI compatible with the vendor U-Boot, or by making the vendor U-Boot compatible with the upstream OpenSBI. On my side, I prefer the latter option as it also keeps the upstream OpenSBI compatible with the (future) upstream U-Boot. I have just published a blog post about how to do that: https://blog.aurel32.net/upstream-opensbi-spacemit-k1.html Regards Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net