From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 08DD43C7DF1 for ; Mon, 27 Apr 2026 13:20:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777296058; cv=none; b=mnstqRLdE3Z7Pb1i6iDJ7JYBlOd+7WlXGMzrx+xkIBqivfPR09ivFKmMutOB1dDPh67lsLn2FE5c4QSpA2Tmpmh6Gn3GQAUDPHg3SqQG1MuONKUcA+WBdv79eyy2OV4H+IhiGgAv1fmXv9fXEyZG10wW6isYaBLatO5+2MgxmbM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777296058; c=relaxed/simple; bh=mo+Pje5KJOlOqFaHKi/Clt9VDeqhXPrPNpSe+ce+T8c=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=s4AqSCg8S5N3NrJf9fjI/tTKq9SRMIRSNOqxUpMeCScJmL7yXrpN8kxDDv8L7UOw+Teu37cSd+P65DJPMc0EQLcIMFvDrh9rK7f0yzjkfnwFvaVKqmoodIYKVlVGs8ImeskGnQfDh5HgaxdKXcIBQGSCJ66R0GCQrGCS5SqllPo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=hJqWE0Q7; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="hJqWE0Q7" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D183D22EA; Mon, 27 Apr 2026 06:20:49 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 03C303F763; Mon, 27 Apr 2026 06:20:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777296055; bh=mo+Pje5KJOlOqFaHKi/Clt9VDeqhXPrPNpSe+ce+T8c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=hJqWE0Q7amhIE6ewRnSqqOogbZ3siw+W/z9/fboWezLK/JGBf1Tj1uBpTKwbpCbYM HpBMSzKsx/byXHh0MBH28m2pTa8GShTmU5QKAaHYwdwhbtCDlAUQNVE/5khbLnS2Qn rAr1M327V2nB3Y7SyR4O26CNXi67TV5hfziJOuyg= Date: Mon, 27 Apr 2026 14:20:41 +0100 From: Catalin Marinas To: Pengjie Zhang Cc: will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, mrigendra.chaubey@gmail.com, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, zhanjie9@hisilicon.com, zhenglifeng1@huawei.com, lihuisong@huawei.com, yubowen8@huawei.com, linhongye@h-partners.com, linuxarm@huawei.com, wangzhi12@huawei.com Subject: Re: [PATCH v2] arm64: smp: Do not mark secondary CPUs possible under nosmp Message-ID: References: <20260423134654.4178271-1-zhangpengjie2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260423134654.4178271-1-zhangpengjie2@huawei.com> On Thu, Apr 23, 2026 at 09:46:54PM +0800, Pengjie Zhang wrote: > Under nosmp (maxcpus=0), arm64 never brings up secondary CPUs. > > However, arm64 still enumerates firmware-described CPUs during SMP > initialization, which can leave secondary CPUs visible to > for_each_possible_cpu() users even though they never reach the > bringup path in this configuration. > > This is not just a cosmetic mask mismatch: code iterating over > possible CPUs may observe secondary CPU per-CPU state that is never > fully initialized under nosmp. I'm fine with the patch in principle but I fail to see why it is not mostly cosmetic. If we have possible & !present CPUs (there's another thread around cpuhp_smt_enable() to allow this combination on arm64), get_cpu_device() would return NULL and the core code is supposed to handle this. What other per-CPU state should be initialised for a possible CPU but it is not without this patch? -- Catalin