From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8139E37B40A for ; Thu, 16 Apr 2026 06:54:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776322468; cv=none; b=VnSvnVqdUaQcP6uCZRIqBDk2dhfnZKwXVb3gHYrBxebcFiD//iaSyL/ljd+qL93lqwljPJcm7bFTRjRitE/3SGLExOHQNA4MsHgfKojjfYtZxNXuEfMjjW6FVuS+szCgEzgO2Q5Grf6mLJlv2Yj892QkCscCUBHw2b/t4B9UGp8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776322468; c=relaxed/simple; bh=uqD/dt6liEaUaBZRxwhT8lly7nB6+86rIhs4gDGLvFM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=sY8KRPv9lyngs3jA/PrZ2B5eE9Imoal/zzwaftt9yr0sw/adDzRjNa6WTzHjBVIy6cuEZYvbjagW3bN2XjW6NWCrnwm/HPRdiG1ofEnqoYULtwqoe10ij7YS69t1+JrlvyDbs9jrtQ09IFsrJFuMXDFfqEdRkpvxDS6AP54rnHE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=DFUsjQ1m; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="DFUsjQ1m" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0C68F25E9; Wed, 15 Apr 2026 23:54:20 -0700 (PDT) Received: from e129823.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3A6FA3F7D8; Wed, 15 Apr 2026 23:54:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776322465; bh=uqD/dt6liEaUaBZRxwhT8lly7nB6+86rIhs4gDGLvFM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=DFUsjQ1m2zhRIw4w1aAVNWMoy5NZM+jg0re5Ugxqx0mvooWG3J0q7WFLP+rbyq7uQ 8al3mPjbBQIcApP7zOkeK7LOIazLmIlhEVytUA+kGaJP2/xdrFByz1UupNyT90VVJx kpq1Dv4d1f8dF/3z9Af90od6BZ5UT1Qto0cbbJ+k= Date: Thu, 16 Apr 2026 07:54:21 +0100 From: Yeoreum Yun To: Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com Subject: Re: [PATCH v5 04/12] coresight: etm4x: exclude ss_status from drvdata->config Message-ID: References: <20260415165528.3369607-1-yeoreum.yun@arm.com> <20260415165528.3369607-5-yeoreum.yun@arm.com> <778a826b-918d-4f7c-95a9-1cdb013618d8@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <778a826b-918d-4f7c-95a9-1cdb013618d8@oss.qualcomm.com> Hi Jie, > > > On 4/16/2026 12:55 AM, Yeoreum Yun wrote: > > The purpose of TRCSSCSRn register is to show status of > > the corresponding Single-shot Comparator Control and input supports. > > That means writable field's purpose for reset or restore from idle status > > not for configuration. > > > > Therefore, exclude ss_status from drvdata->config, move it to etm4x_caps > > and rename it to ss_smp. > > > > This includes remove TRCSSCRn from configurable item and > > remove saving in etm4_disable_hw(). > > > > Signed-off-by: Yeoreum Yun > > --- > > .../hwtracing/coresight/coresight-etm4x-cfg.c | 1 - > > .../coresight/coresight-etm4x-core.c | 19 ++++++------------- > > .../coresight/coresight-etm4x-sysfs.c | 7 ++----- > > drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++- > > 4 files changed, 14 insertions(+), 20 deletions(-) > > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > > index c302072b293a..d14d7c8a23e5 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > > @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, > > off_mask = (offset & GENMASK(11, 5)); > > do { > > CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); > > - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); > > CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); > > } while (0); > > } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) { > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > > index b2b092a76eb5..f55338a4989d 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > > @@ -91,7 +91,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) > > const struct etmv4_caps *caps = &drvdata->caps; > > return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp && > > - (drvdata->config.ss_status[n] & TRCSSCSRn_PC); > > + (caps->ss_cmp[n] & TRCSSCSRn_PC); > > } > > u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) > > @@ -573,11 +573,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); > > for (i = 0; i < caps->nr_ss_cmp; i++) { > > - /* always clear status bit on restart if using single-shot */ > > - if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) > > - config->ss_status[i] &= ~TRCSSCSRn_STATUS; > > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); > > - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); > > + /* always clear status and pending bits on restart if using single-shot */ > > + etm4x_relaxed_write32(csa, 0x0, TRCSSCSRn(i)); > > if (etm4x_sspcicrn_present(drvdata, i)) > > etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); > > } > > @@ -1055,12 +1053,6 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata) > > etm4_disable_trace_unit(drvdata); > > - /* read the status of the single shot comparators */ > > - for (i = 0; i < caps->nr_ss_cmp; i++) { > > - config->ss_status[i] = > > - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > > - } > > - > > /* read back the current counter values */ > > for (i = 0; i < caps->nr_cntr; i++) { > > config->cntr_val[i] = > > @@ -1503,8 +1495,9 @@ static void etm4_init_arch_data(void *info) > > */ > > caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); > > for (i = 0; i < caps->nr_ss_cmp; i++) { > > - drvdata->config.ss_status[i] = > > - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > > + caps->ss_cmp[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > > + caps->ss_cmp[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV | > > + TRCSSCSRn_DA | TRCSSCSRn_INST); > > Just re-go through this patch and had a question here: > > I’m not sure whether this new change should be documented in the ABI, given > that the TRCSSCSRn_STATUS bit is masked. In my opinion, this change breaks > the existing ABI description. > > Description from the ABI document: > > What: /sys/bus/coresight/devices/etm/sshot_status > Date: December 2019 > KernelVersion: 5.5 > Contact: Mathieu Poirier > Description: (Read) Print the current value of the selected single > shot status register. But, as I mentioned another thread: - https://lore.kernel.org/all/ad5yV2FoNbGGLE6R@e129823.arm.com/ Till now, sysfs doesn't show the *current value* of the single shot state since the config->ss_status is updated enabled/disabled sysfs session. an I think once the session is disabled, other status bits (currently STATUS and PENDING bits) don't have any meaning. I think it's enough to change the doc's Description for this. Any thought? -- Sincerely, Yeoreum Yun