Re: [PATCH v2 2/3] pwm: rp1: Add RP1 PWM controller driver

[Andrea della Porta <andrea.porta@suse.com>]

Hi Uwe,

On 15:48 Thu 16 Apr     , Uwe Kleine-König wrote:
> Hello Andrea,
> 
> one thing I forgot to ask: Is there a public reference manual covering
> the hardware. If yes, please add a link at the top of the driver.

Sort of, it's already reported in this driver top comment (Datasheet: tag).
The PWM controller is part of the RP1 chipset and you can find its description
under the PWM section. This is not a full-fledged datasheet but the registers
for the controller are somewhow documented.

> 
> On Thu, Apr 16, 2026 at 12:30:43PM +0200, Andrea della Porta wrote:
> > On 19:31 Fri 10 Apr     , Uwe Kleine-König wrote:
> > > I assume there is a glitch if I update two channels and the old
> > > configuration of the first channel ends while I'm in the middle of
> > > configuring the second?
> > 
> > The configuration registers are per-channel but the update flag is global.
> > I don't have details of the hw insights, my best guess is that anything that
> > you set in the registers before updating the flag will take effect, so there
> > should be no glitches.
> 
> Would be great if you could test that. (Something along the lines of:
> configure a very short period and wait a bit to be sure the short
> configuration is active. Configure something with a long period and wait
> shortly to be sure that the long period started, then change the duty,
> toggle the update bit and modify a 2nd channel without toggling update
> again. Then check the output of the 2nd channel after the first
> channel's period ended.

I stand corrected here: after some more investigation it seems that only the
enable/disable (plus osme other not currently used registers) depends on the
global update flag, while the period and duty per-channel registers are
independtly updatable while they are latched on the end of (specific channel)
period strobe.
I'd say that this should avoid any cross-channel glitches since they are managed
independently. Unfortunately I'm not able to test this with my current (and
rather old) equipment, this would require at least an external trigger channel.
Regarding the setup of a new value exactly during the strobe: I think this is
quite hard to achieve.

> 
> > > > +	if (ticks > U32_MAX)
> > > > +		ticks = U32_MAX;
> > > > +	wfhw->period_ticks = ticks;
> > > 
> > > What happens if wf->period_length_ns > 0 but ticks == 0?
> > 
> > I've added a check, returning 1 to signal teh round-up, and a minimum tick of 1
> > in this case.
> 
> Sounds good. Are you able to verify that there is no +1 missing in the
> calculation, e.g. using 1 as register value really gives you a period of
> 1 tick and not 2?

You are right. The scope reveals there's always one extra (low signal) tick at the
end of each period. Let's say that teh user want 10 tick period, we have to use
9 instead to account for the extra tick at the end, so that the complete period
contains that extra tick?
This also means that if we ask for 100% duty cycle, the output waveform will
have the high part of the signal lasting one tick less than expected.a I guess
this is the accepted compromise.

OTOH, the minimum tick period would be 2 tick, less than that will otherwise
degenerate in a disabled channel.

> 
> > > > +	if (wf->duty_offset_ns + wf->duty_length_ns >= wf->period_length_ns) {
> > > 
> > > The maybe surprising effect here is that in the two cases
> > > 
> > > 	wf->duty_offset_ns == wf->period_length_ns and wf->duty_length_ns == 0
> > > 
> > > and
> > > 	
> > > 	wf->duty_length_ns == wf->period_length_ns and wf->duty_offset_ns == 0
> > > 
> > > you're configuring inverted polarity. I doesn't matter technically
> > > because the result is the same, but for consumers still using pwm_state
> > > this is irritating. That's why pwm-stm32 uses inverted polarity only if
> > > also wf->duty_length_ns and wf->duty_offset_ns are non-zero.
> 
> Please align to the pwm-stm32 algorithm (as of
> https://patch.msgid.link/c5e7767cee821b5f6e00f95bd14a5e13015646fb.1776264104.git.u.kleine-koenig@baylibre.com)
> here to decide when to select inverted polarity.

Yep, I did already done when you sent that patch.

> 
> > > > +	}
> > > > +
> > > > +	return 0;
> > > > +
> > > > +err_disable_clk:
> > > > +	clk_disable_unprepare(rp1->clk);
> > > > +
> > > > +	return ret;
> > > > +}
> > > 
> > > On remove you miss to balance the call to clk_prepare_enable() (if no
> > > failed call to clk_prepare_enable() in rp1_pwm_resume() happend).
> > 
> > Since this driver now exports a syscon, it's only builtin (=Y) so
> > it cannot be unloaded.
> > I've also avoided the .remove callback via .suppress_bind_attrs.
> 
> Oh no, please work cleanly here and make the driver unbindable. This
> yields better code quality and also helps during development and
> debugging.

I wish to, but the issue here is that this driver exports a syscon via 
of_syscon_register_regmap() which I think doesn't have the unregister
counterpart. So the consumer will break in case we can unbind/unload
the module and the syscon will leak. 
If you have any alternative I'll be glad to discuss.

Many thanks,
Andrea

> 
> Best regards
> Uwe