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Fri, 17 Apr 2026 21:56:45 -0700 Received: from nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Fri, 17 Apr 2026 21:56:44 -0700 Date: Fri, 17 Apr 2026 21:56:42 -0700 From: Nicolin Chen To: "Tian, Kevin" CC: "joro@8bytes.org" , "jgg@nvidia.com" , "will@kernel.org" , "robin.murphy@arm.com" , "baolu.lu@linux.intel.com" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "xueshuai@linux.alibaba.com" Subject: Re: [PATCH rc v6] iommu: Fix nested pci_dev_reset_iommu_prepare/done() Message-ID: References: <20260407194644.171304-1-nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4D:EE_|DS0PR12MB7512:EE_ X-MS-Office365-Filtering-Correlation-Id: 92502749-c071-4dcf-cdfc-08de9d06eaac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|22082099003|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /pnO6npDOxYyUXzFqneDoNTs1TtRnXotd4XQxAjhmRQyMD1f0+Dt0f8iyDdkoKVcGmY9wkxCACKl/xeoGDxiw1s2rcCcV9sThtQ5ro3vHtDCXqX1tM2zwSKrKZLaJu2ap5cawygZ86P6tUaj2x7PUVvZ93X3GgKv+9TJdoQexJcS0Ug6FogshCzo+gL78lKo+0aL2yu3PDw44yJyoZ1zbr98GTC2fx+w9Cpr29+Ovv5Tq01qPAlFfy3vrSky2xl+qM6nF5QVaWv82K0lBYEz9vbn4d/VAHnlfeq4AvVAvfdmyu/Y/i+PUEapoJaV3N/V86hdcehEhskIoR9IR8a4H0cBYg0dGtoinmphywLA5GotqC5LyTutm9/vGAfQCLJYEHrS0MQ/fMptY+vye6HAmvZE9QsW71LoOpw/mbFT3Kh3ZZHtG9j62tuwblLWIt2l X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2026 04:56:56.4468 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92502749-c071-4dcf-cdfc-08de9d06eaac X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7512 On Fri, Apr 17, 2026 at 02:44:41PM -0700, Nicolin Chen wrote: > On Fri, Apr 17, 2026 at 08:24:27AM +0000, Tian, Kevin wrote: > > one is that iommu_detach_device_pasid() is not blocked which can trigger > > devtlb invalidation in middle of reset. but it cannot fail. so the right fix is > > to skip the blocked device in __iommu_remove_group_pasid(). > > Yea, squashing this: > @@ -3556,3 +3559,4 @@ static void __iommu_remove_group_pasid(struct iommu_group *group, > for_each_group_device(group, device) { > - if (device->dev->iommu->max_pasids > 0) > + /* Device might be already detached for a device recovery */ > + if (!device->blocked && device->dev->iommu->max_pasids > 0) > iommu_remove_dev_pasid(device->dev, pasid, domain); > > > another is a use-after-free concern upon iommu_detach_device() in > > middle of reset. In my thinking it will trigger WARN_ON before any UAF: > > > > static void __iommu_group_set_domain_nofail(struct iommu_group *group, > > struct iommu_domain *new_domain) > > { > > WARN_ON(__iommu_group_set_domain_internal( > > group, new_domain, IOMMU_SET_DOMAIN_MUST_SUCCEED)); > > } > > Yes. > > > but I haven't got time to think about the fix carefully. > > I think we could squash this: > > @@ -2469,9 +2469,2 @@ static int __iommu_group_set_domain_internal(struct iommu_group *group, > > - /* > - * This is a concurrent attach during device recovery. Reject it until > - * pci_dev_reset_iommu_done() attaches the device to group->domain. > - */ > - if (group->recovery_cnt) > - return -EBUSY; > - On a second thought, we may not simply drop this -- IIRC, we added it particularly to fence a case where gdevs share the same RID or some corner case like that? In a conservative way, we can still reject concurrent attach while allowing the detach case: + /* + * This is a concurrent attach during device recovery. Reject it until + * pci_dev_reset_iommu_done() attaches the device to group->domain. + * + * Note: still allow MUST_SUCCEED callers (detach/teardown) through to + * avoid UAF on domain release paths. + */ + if (group->recovery_cnt && !(flags & IOMMU_SET_DOMAIN_MUST_SUCCEED)) + return -EBUSY; + In the detach path, it'll move forward and skip per gdev->blocked inside the for_each_group_device() and defer the attach to done(). Thanks Nicolin > @@ -2484,2 +2477,10 @@ static int __iommu_group_set_domain_internal(struct iommu_group *group, > for_each_group_device(group, gdev) { > + /* > + * Skip devices under recovery: they are already attached to > + * group->blocking_domain at the hardware level. When their > + * reset completes, pci_dev_reset_iommu_done() will re-attach > + * them to the updated group->domain. > + */ > + if (gdev->blocked) > + continue; > ret = __iommu_device_set_domain(group, gdev->dev, new_domain, > @@ -2513,2 +2514,4 @@ static int __iommu_group_set_domain_internal(struct iommu_group *group, > break; > + if (gdev->blocked) > + continue; > /* > > > > the last one is trivial that goto and guard() shouldn't be mixed in one > > function according to the cleanup guidelines. > > I don't think this is mixing. The guard is protecting the entire > routine including those goto paths. So there isn't any goto path > that is outside the mutex. > > > Reviewed-by: Kevin Tian > > Thanks! > Nicolin