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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12da8b8fbc4sm4347880c88.4.2026.04.20.19.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2026 19:56:01 -0700 (PDT) Date: Tue, 21 Apr 2026 10:55:56 +0800 From: Shawn Guo To: Manivannan Sadhasivam Cc: Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Qiang Yu , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] PCI: qcom: Disable ASPM L0s for SA8775P Message-ID: References: <20260419093934.1223027-1-shengchao.guo@oss.qualcomm.com> <453jc2ff65zdn3yahdwkdh2uqzz2coi4kv3siqfygfgmfd3v4w@4dkwj3s4dkfp> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <453jc2ff65zdn3yahdwkdh2uqzz2coi4kv3siqfygfgmfd3v4w@4dkwj3s4dkfp> X-Authority-Analysis: v=2.4 cv=KfbidwYD c=1 sm=1 tr=0 ts=69e6e743 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=A0J8VqqiQ3YToNBSq38A:9 a=CjuIK1q_8ugA:10 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-ORIG-GUID: fNslf3K_LptLdn4JcqJtBlb_N9Tvl-Zp X-Proofpoint-GUID: fNslf3K_LptLdn4JcqJtBlb_N9Tvl-Zp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIxMDAyNyBTYWx0ZWRfX2DxfXoecs8Q8 mzYR/+6Uzf7o62GK6HihwtxL+/GmqEUI6j7VDdAwX8JK1HRVYNhUmvhfsW0vDN/ApweIYoPWmE0 LwppvpEWTvEpD+4c4zu/JrrodPEyENUTi48CxahHVag51W2bFlWCqGV8dLdzUs1d6/PWxV22mdi 3Jb0KD9FhEry/OfOeL8I/10kDJlgHB4z6bj2dUA5xJr7VjTkW3brN+dM+FkhEXM0uMZmhr+4na4 j3PfRSq+C3o/iAzEYzFr32lZTOlB8ZL2YdQvPmqo5mVIbvKdVoYUU4TDnK5EMrixW4qxhfWW04M ejKEBtkPqUSIc4JVOeJFRmr3xdoC/EoSayMTCNiBXjATcwCUkloIGOfIZxIaNhcOqSXpv2+oMiZ CXSvHqdSNiQqZgmYLqUIMkweyHWU4PbsrdtGkZCrbt323ggzIsiRsHQpdfY8tGIkzTM9vIpMqKS SQuc1sEcoV7mwBpus+w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-20_05,2026-04-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 spamscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210027 On Mon, Apr 20, 2026 at 12:08:25PM +0530, Manivannan Sadhasivam wrote: > On Sun, Apr 19, 2026 at 05:39:34PM +0800, Shawn Guo wrote: > > Commit f5cd8a929c82 ("PCI: dwc: Remove MSI/MSIX capability for Root Port > > if iMSI-RX is used as MSI controller") removed MSI/MSI-X capabilities > > from the Root Port on platforms using iMSI-RX (including SA8775P, which > > has no msi-parent/msi-map in DT). This causes PME and AER service > > drivers to fall back from MSI to INTx. > > > > With INTx-based PME active, the QCN9100 modem endpoint sends PME messages > > during D-state transitions early in boot. The level-triggered INTx > > assertion coincides with ASPM L0s exit sequencing on SA8775P hardware, > > causing Data Link Layer Replay Timer Timeout errors on both sides of the > > link. > > > > How did you conclude that INTx collides with ASPM L0s exit sequence? Also, > AFAIK, L0s is supported and work well on this chipset. > > What we are dealing with could be the board specific issue. I just got looped into an internal discussion. The issue seems to be refgen voting related, so likely affects all Lemans (and Monaco) boards with PCIe enabled. Before a proper fix is available, 'pcie_aspm=off' on kernel cmdline is suggested as a temporary workaround. > > [ 13.069528] pcieport 0000:00:00.0: PME: Signaling with IRQ 332 > > [ 13.082436] pcieport 0000:00:00.0: AER: enabled with IRQ 332 > > [ 13.082447] pcieport 0000:00:00.0: AER: Correctable error message received from 0000:01:00.0 > > [ 13.101347] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID) > > [ 13.111281] pci 0000:01:00.0: device [17cb:1103] error status/mask=00001000/0000e000 > > [ 13.111284] pci 0000:01:00.0: [12] Timeout > > [ 13.111313] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0 > > [ 13.130512] pcieport 0000:00:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID) > > [ 13.130514] pcieport 0000:00:00.0: device [17cb:0115] error status/mask=00001000/0000e000 > > [ 13.130516] pcieport 0000:00:00.0: [12] Timeout > > > > Fix the PCIe regression on SA8775P/Lemans platform by adding no_l0s = true > > to cfg_1_34_0 for SA8775P, so that PCI_EXP_LNKCAP_ASPM_L0S is cleared from > > the Root Port and ASPM L0s is prevented from being negotiated. > > > > No. This is not the correct fix. If we identify if this is a board issue, we > need to disable L0s selectively using 'pcie,no-aspm-l0s' DT property defined in > the Root Port DT node. > > > Fixes: f5cd8a929c82 ("PCI: dwc: Remove MSI/MSIX capability for Root Port if iMSI-RX is used as MSI controller") > > Assisted-by: Claude:claude-4-6-sonnet > > Ok, this seems to be an AI slop. INTx is triggered through in-band messages and > the link should be in L0 so that an endpoint can transmit these. So there is no > way it could collide with L0s exit sequence as the link being in L0 is the > pre-requisite for triggering INTx. Thank you for the insight! Indeed, I was asking help from AI as I do not have too much expertise on PCIe ;) Shawn