From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C888E382373 for ; Wed, 22 Apr 2026 17:16:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776878173; cv=none; b=sJS4X/ow/lJwqpo3eSolg1iiW5To1TJnVsvkVVL5Qmjmkc7rOd/5OBwzBIIEOU4iCrQbTYGZ0uDpDm+ivUXYCf8lsefFNdPHoWO+JtNDPnW26NTAV/8enj/gEcrqzAxcmZOAQuY5/jczhxYmaWF9ROPPQLUk5zoM/kp/wkUZfK8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776878173; c=relaxed/simple; bh=LVmvJGYdkwynjW2RgSaR1jTwKn3MAEF8tFIFGVj7kBc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=sS4t4OgnOPVEsR5HKivrBgU/06pVoC6eqBloMxlS5JA0VZ0IoX9OV/X8ffsUT+rlfOWTCCXM+Smmwbl7o461Yt2VioLS4oMCZ8bmY16eQGbpwneLQ0ynwm3BlO5jxCcKIl/OH4YJMdkmRBuy6HjYuHEV00Q8RvToFCfJ23ThRbI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=rUj0B2iM; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="rUj0B2iM" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EACA31F37; Wed, 22 Apr 2026 10:16:02 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2CB8E3F641; Wed, 22 Apr 2026 10:16:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776878168; bh=LVmvJGYdkwynjW2RgSaR1jTwKn3MAEF8tFIFGVj7kBc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=rUj0B2iM/oQRJ+TaA66CaUWXCrSplp8LiRNBnfwE+NG5idlz4LhH5m2UpkdxkRj6W JpinZJOCVnSPpckKW2B0SpY4ry2bJfcvfQO2gG/b9eCpLGaP5UCI9wYorgYLRxbSQJ EIFpRRaG+cNce+22qoUVYf/4ziOe39qbn+M/eRtQ= Date: Wed, 22 Apr 2026 18:16:02 +0100 From: Catalin Marinas To: Pengjie Zhang Cc: will@kernel.org, maz@kernel.org, timothy.hayes@arm.com, lpieralisi@kernel.org, mrigendra.chaubey@gmail.com, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, zhanjie9@hisilicon.com, zhenglifeng1@huawei.com, lihuisong@huawei.com, yubowen8@huawei.com, linhongye@h-partners.com, linuxarm@huawei.com, wangzhi12@huawei.com Subject: Re: [PATCH] arm64: smp: Limit nr_cpu_ids under nosmp Message-ID: References: <20260422095831.2926775-1-zhangpengjie2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260422095831.2926775-1-zhangpengjie2@huawei.com> On Wed, Apr 22, 2026 at 05:58:31PM +0800, Pengjie Zhang wrote: > Under nosmp (maxcpus=0), arm64 never brings up secondary CPUs. > > However, arm64 still enumerates firmware-described CPUs during SMP > initialization, so secondary CPUs can remain visible to > for_each_possible_cpu() users even though they never reach the > bringup path in this configuration. > > This is not just a cosmetic mask mismatch: code iterating over > possible CPUs may observe secondary CPU per-CPU state that is never > fully initialized under nosmp. > > Limit nr_cpu_ids to 1 in arch_disable_smp_support() so that > secondary CPUs are not set up on arm64 when nosmp/maxcpus=0 is in > effect. > > Signed-off-by: Pengjie Zhang > --- > arch/arm64/kernel/smp.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c > index 1aa324104afb..cc34c68871e9 100644 > --- a/arch/arm64/kernel/smp.c > +++ b/arch/arm64/kernel/smp.c > @@ -435,6 +435,15 @@ static void __init hyp_mode_check(void) > } > } > > +void __init arch_disable_smp_support(void) > +{ > + /* > + * Under nosmp/maxcpus=0, only the boot CPU can ever be brought up. > + * Limit nr_cpu_ids so that secondary CPUs are never set up. > + */ > + set_nr_cpu_ids(1); > +} I don't think that's the right fix. We don't have anything like the x86 ioapic to disable in this function, so no need to implement it. If nr_cpu_ids must be 1 with nosmp/maxcpus=0, I'd rather do this in the generic code. It need some alignment with other architectures if we are to do this early. IOW, is nosmp equivalent to nr_cpus=1? In the meantime, for arm64, we can do something like below and let the generic code set nr_cpu_ids() via start_kernel() -> setup_nr_cpu_ids(). -------------8<------------------- diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 1aa324104afb..7364481cc03a 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -754,6 +754,13 @@ void __init smp_init_cpus(void) return; } + /* + * For the nosmp/maxcpus=0 case, do not mark the secondary CPUs + * possible. + */ + if (!setup_max_cpus) + return; + /* * We need to set the cpu_logical_map entries before enabling * the cpus so that cpu processor description entries (DT cpu nodes