From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from hall.aurel32.net (hall.aurel32.net [195.154.119.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 990CC2F2914 for ; Thu, 23 Apr 2026 20:49:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.154.119.183 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776977381; cv=none; b=ckzNRJRbyjRGZ27YhyE/rhksTTNMuBeQpuVzTex/TQzCdckac4XXHUExxFPrYvqvoi7ClcUMQVGxGwYvQ8kaI/W90B8B7g+Lgd3Twf/gt1l6vH1GeyV6r1LqrcC6Yo7Q6RgyFHZ9LWztUiG0qXlnKCLw7C87sc+MFLfARefx2g0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776977381; c=relaxed/simple; bh=rOFxE0rCe7AqbofjLem5DtJ6i/vJCHJtNhxaJxNk+kk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=OmqcFKBSksVPVuikNqchGr190YrIoln/0MMiqkpNnFIItSChOBxcSf6j0j9Jk3fQbQK6X2GSmj2R8vyncWvlstRKU6oJxycwSbCA9G0K4zgwuceBjZX/79k5mwcnrUE+uU3Xy2NGsTc9oVbTGRFxlLF7VGA7q478diFBYYnz4bg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=aurel32.net; spf=pass smtp.mailfrom=aurel32.net; dkim=pass (2048-bit key) header.d=aurel32.net header.i=@aurel32.net header.b=ZkYgsfYE; arc=none smtp.client-ip=195.154.119.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=aurel32.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aurel32.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aurel32.net header.i=@aurel32.net header.b="ZkYgsfYE" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=In-Reply-To:Content-Type:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Content-Transfer-Encoding:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=I7X6zJHC5DYuCh8sgrWG+KoRBJR5g583wwIpVUm7vX4=; b=ZkYgsfYER5/VHsabiDSp6NdOU0 t0QV1P3f3v9LK1vWOTSS4iGK4DAzyu8Cctel6DpwCtfgi6ecB4WMisVN8NOkXQTe0Oh/U0HqeHxtA +zLSSH25c/KR2CCdC5GcnWywLs16uxfc8BvT3U4GxLc7VIH4gut2vRi5reNlE+Wwskn058O7CTn96 MuDit29eVd1BQiVRU8lKZX1xy1JqrLe9K0Izc23oHYwJdvUmlu705+NDfaZasJiP2qA27srQfSmBA U807XHKvD125OlbHnO9tuDrvIX9nckIe+yMLpo2hXEnxFG3AJkaoEEQAZuDtfXcCj/p0nG2tDZLyW yoGLsQrQ==; Received: from authenticated user by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wG0zC-00000000Mzz-1UXg; Thu, 23 Apr 2026 22:49:22 +0200 Date: Thu, 23 Apr 2026 22:49:20 +0200 From: Aurelien Jarno To: Samuel Holland Cc: Troy Mitchell , Vivian Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC] riscv: disable local interrupts and stop other CPUs before restart Message-ID: Mail-Followup-To: Samuel Holland , Troy Mitchell , Vivian Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260311-v7-0-rc1-rv-dis-int-before-restart-v1-1-bc46b4351cac@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.13 (2024-03-09) Hi, On 2026-03-16 08:19, Samuel Holland wrote: > Hi Troy, > > On 2026-03-16 2:23 AM, Troy Mitchell wrote: > >> I think the reason we ended up with the "unsafe" implementations of the > >> reboot/shutdown functions is that on the backend it is usually SBI SRST > >> calls, which can protect itself from other CPUs and interrupts. Since on > >> K1 we're going to be poking I2C directly, we run into the problem > >> described above. So all of these should disable interrupts and stop > >> other CPUs before calling the handlers, and can't assume the handlers > >> are all SBI SRST. > > Yes, we cannot assume that all platforms rely on this. > > Why isn't K1 using the SBI SRST extension? Resetting the platform from S-mode > directly causes problems if you ever want to run another supervisor domain (for > example a TEE or EFI runtime services), which may need to clean up before a > system reset. > > As you mention, other platforms use the standard SBI SRST interface, event if > they need to poke a PMIC to perform a system reset. Is there something > preventing K1 from following this path? I went this path and submitted a patchset to OpenSBI mailing list doing that: https://lore.kernel.org/opensbi/20260419150857.2705843-1-aurelien@aurel32.net/T/#t Regards Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net