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From: Bjorn Andersson <andersson@kernel.org>
To: Linlin Zhang <linlin.zhang@oss.qualcomm.com>
Cc: Konrad Dybcio <konradybcio@kernel.org>,
	linux-arm-msm@vger.kernel.org,  linux-kernel@vger.kernel.org,
	Neeraj Soni <neeraj.soni@oss.qualcomm.com>,
	 Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Subject: Re: [PATCH v2 2/3] soc: qcom: ice: Enable PM runtime for ICE driver
Date: Thu, 7 May 2026 16:19:47 -0500	[thread overview]
Message-ID: <af0Bsv-OFs3rmbQS@baldur> (raw)
In-Reply-To: <20260507112626.2527413-1-linlin.zhang@oss.qualcomm.com>

On Thu, May 07, 2026 at 04:26:24AM -0700, Linlin Zhang wrote:

I only got 2 of the 3 patches, and no cover letter. I can see in the
mail headers that you have:

 X-Mailer: git-send-email 2.25.1

Use b4 to avoid this kind of mistakes.

Regards,
Bjorn

> The QCOM ICE driver manages the ICE core clock through direct calls to
> clk_prepare_enable() and clk_disable_unprepare(), which limits integration
> with platforms that rely on firmware-managed resources or platform-specific
> power management mechanisms.
> 
> Replace direct clock management with runtime PM support by moving clock
> enable and disable into runtime PM callbacks. Use
> pm_runtime_resume_and_get() and pm_runtime_put_sync() in qcom_ice_resume()
> and qcom_ice_suspend() to drive power state transitions, and enable runtime
> PM in qcom_ice_probe().
> 
> Reviewed-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
> Reviewed-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> Signed-off-by: Linlin Zhang <linlin.zhang@oss.qualcomm.com>
> ---
>  drivers/soc/qcom/ice.c | 58 ++++++++++++++++++++++++++++++++++++++----
>  1 file changed, 53 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
> index b203bc685cad..6f9d679b530c 100644
> --- a/drivers/soc/qcom/ice.c
> +++ b/drivers/soc/qcom/ice.c
> @@ -16,6 +16,7 @@
>  #include <linux/of.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
>  
>  #include <linux/firmware/qcom/qcom_scm.h>
>  
> @@ -310,8 +311,8 @@ int qcom_ice_resume(struct qcom_ice *ice)
>  	struct device *dev = ice->dev;
>  	int err;
>  
> -	err = clk_prepare_enable(ice->core_clk);
> -	if (err) {
> +	err = pm_runtime_resume_and_get(dev);
> +	if (err < 0) {
>  		dev_err(dev, "failed to enable core clock (%d)\n",
>  			err);
>  		return err;
> @@ -323,7 +324,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume);
>  
>  int qcom_ice_suspend(struct qcom_ice *ice)
>  {
> -	clk_disable_unprepare(ice->core_clk);
> +	pm_runtime_put_sync(ice->dev);
>  	ice->hwkm_init_complete = false;
>  
>  	return 0;
> @@ -716,24 +717,69 @@ EXPORT_SYMBOL_GPL(devm_of_qcom_ice_get);
>  
>  static int qcom_ice_probe(struct platform_device *pdev)
>  {
> +	struct device *dev = &pdev->dev;
>  	struct qcom_ice *engine;
>  	void __iomem *base;
> +	int ret;
>  
>  	base = devm_platform_ioremap_resource(pdev, 0);
>  	if (IS_ERR(base)) {
> -		dev_warn(&pdev->dev, "ICE registers not found\n");
> +		dev_warn(dev, "ICE registers not found\n");
>  		return PTR_ERR(base);
>  	}
>  
> -	engine = qcom_ice_create(&pdev->dev, base);
> +	engine = qcom_ice_create(dev, base);
>  	if (IS_ERR(engine))
>  		return PTR_ERR(engine);
>  
>  	platform_set_drvdata(pdev, engine);
>  
> +	ret = devm_pm_runtime_enable(dev);
> +	if (ret) {
> +		dev_warn(dev, "Enable runtime PM failed, ret: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = pm_runtime_resume_and_get(dev);
> +	if (ret < 0) {
> +		dev_warn(dev, "Runtime PM fails to resume, ret: %d\n", ret);
> +		return ret;
> +	}
> +
>  	return 0;
>  }
>  
> +static void qcom_ice_remove(struct platform_device *pdev)
> +{
> +	pm_runtime_put_sync(&pdev->dev);
> +}
> +
> +static int ice_runtime_resume(struct device *dev)
> +{
> +	struct qcom_ice *ice = dev_get_drvdata(dev);
> +	int err = 0;
> +
> +	err = clk_prepare_enable(ice->core_clk);
> +	if (err) {
> +		dev_err(dev, "failed to enable core clock (%d)\n",
> +			err);
> +	}
> +
> +	return err;
> +}
> +
> +static int ice_runtime_suspend(struct device *dev)
> +{
> +	struct qcom_ice *ice = dev_get_drvdata(dev);
> +
> +	clk_disable_unprepare(ice->core_clk);
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops ice_pm_ops = {
> +	SET_RUNTIME_PM_OPS(ice_runtime_suspend, ice_runtime_resume, NULL)
> +};
> +
>  static const struct of_device_id qcom_ice_of_match_table[] = {
>  	{ .compatible = "qcom,inline-crypto-engine" },
>  	{ },
> @@ -742,8 +788,10 @@ MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table);
>  
>  static struct platform_driver qcom_ice_driver = {
>  	.probe	= qcom_ice_probe,
> +	.remove = qcom_ice_remove,
>  	.driver = {
>  		.name = "qcom-ice",
> +		.pm = &ice_pm_ops,
>  		.of_match_table = qcom_ice_of_match_table,
>  	},
>  };
> -- 
> 2.34.1
> 

  parent reply	other threads:[~2026-05-07 21:19 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-07 11:26 [PATCH v2 2/3] soc: qcom: ice: Enable PM runtime for ICE driver Linlin Zhang
2026-05-07 11:26 ` [PATCH v2 3/3] soc: qcom: ice: Add SCMI support for sa8255p based targets Linlin Zhang
2026-05-07 21:19 ` Bjorn Andersson [this message]
2026-05-11 12:15   ` [PATCH v2 2/3] soc: qcom: ice: Enable PM runtime for ICE driver Linlin Zhang

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