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[34.124.234.44]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bae788e042sm7614555ad.79.2026.05.07.15.30.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2026 15:30:19 -0700 (PDT) Date: Thu, 7 May 2026 22:30:14 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: Will Deacon , Joerg Roedel , Jean-Philippe Brucker , Robin Murphy , Jason Gunthorpe , Catalin Marinas , =?utf-8?Q?Miko=C5=82aj?= Lenczewski , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits Message-ID: References: <20260503135413.1108138-1-nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260503135413.1108138-1-nicolinc@nvidia.com> On Sun, May 03, 2026 at 06:54:12AM -0700, Nicolin Chen wrote: > HTTU is introduced by utilizing the Dirty Bit Modifier (DBM) in the PTE. > When kernel maps a clean but writable page, it will set PTE_READONLY and > PTE_DBM (aka PTE_WRITE) at the same time. When a write occurs, an HTTU- > capable MMU will automatically clear the PTE_RDONLY bit without software > intervention. > > On the other hand, SMMU has the same HTTU feature, yet it is not enabled > in the SVA CD. As a result, SMMU will not clear the PTE_RDONLY bit while > sharing the CPU page table, resulting in unnecessary stalls. > > Thus, enable CTXDESC_CD_0_TCR_HA and CTXDESC_CD_0_TCR_HD in the SVA CD. > > Suggested-by: Jason Gunthorpe > Signed-off-by: Nicolin Chen > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > index f1f8e01a7e914..1ed8a6f29dc44 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > @@ -92,6 +92,16 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, > > target->data[1] = cpu_to_le64(virt_to_phys(mm->pgd) & > CTXDESC_CD_1_TTB0_MASK); > + > + /* > + * Enable Hardware Access and Dirty updates (DBM) if supported. > + * This is safe to enable by default, as PTE_WRITE and PTE_DBM > + * share the same bit. > + */ > + if (master->smmu->features & ARM_SMMU_FEAT_HA) > + target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HA); > + if (master->smmu->features & ARM_SMMU_FEAT_HD) > + target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HD); IIUC, we should be setting these if IO_PGTABLE_QUIRK_ARM_HD is present? I think the driver maintains a clear distinction between HW capability (FEAT_HA/HD) and feature enablement (IO_PGTABLE_QUIRK_ARM_HD). We set IO_PGTABLE_QUIRK_ARM_HD during S1 domain finalize if IOMMU_HWPT_ALLOC_DIRTY_TRACKING flag is passed. Hence, we should check for that flag OR IO_PGTABLE_QUIRK_ARM_HD before enabling these in CD.. Thanks, Praan